Ross Thompson a1c26a16d6 Cleaned up the linux testbench by removing old code and signals. ... Added back in the csr checking logic. Added code to force timer, external, and software interrupts by using the expected values from qemu's (m/s)cause registers. Still need to prevent wally's timer interrupt.		2021-08-13 14:39:05 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
fpu-testfloat/FMA/tbgen	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
linux-testgen	Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.	2021-08-05 16:49:03 -05:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Cleaned up the linux testbench by removing old code and signals.	2021-08-13 14:39:05 -05:00
src	Added documentation about how the dcache and ptw interact.	2021-08-12 18:05:36 -05:00
testbench	Cleaned up the linux testbench by removing old code and signals.	2021-08-13 14:39:05 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00