Ross Thompson 7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. ... This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.		2021-08-25 21:09:42 -05:00
..
bin
config	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
linux-testgen	Updated linux test bench documenation and scripts.	2021-08-25 10:54:47 -05:00
misc
ppa
regression	Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.	2021-08-25 21:09:42 -05:00
src	Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.	2021-08-25 21:09:42 -05:00
testbench	Removed generate around the dcache memories.	2021-08-25 13:27:26 -05:00
testgen
lint-wally