mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
Switched ExceptionM to dcache to be just exceptions.
Added test bench logic to hold forces until the W stage is unstalled.
This commit is contained in:
Ross Thompson
parent
492b6f0ea4
commit
4f3f26c5cb
@ -489,7 +489,7 @@ add wave -noupdate /testbench/dut/hart/priv/ExtIntM
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add wave -noupdate /testbench/dut/hart/priv/SwIntM
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add wave -noupdate /testbench/ExpectedIntType
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 6} {161345764 ns} 0} {{Cursor 21} {161370961 ns} 0}
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WaveRestoreCursors {{Cursor 6} {161345764 ns} 0} {{Cursor 21} {161370961 ns} 0} {{Cursor 22} {8214887 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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@ -118,19 +118,19 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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@ -304,7 +304,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM r
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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@ -318,10 +317,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
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@ -352,27 +351,25 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
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add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
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@ -441,9 +438,21 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HRDATA
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HSIZED
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset0
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset4
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset5
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset6
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset7
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add wave -noupdate /testbench/dut/hart/ExceptionM
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add wave -noupdate /testbench/dut/hart/PendingInterruptM
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add wave -noupdate /testbench/dut/hart/TrapM
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 6} {8568901 ns} 0}
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WaveRestoreCursors {{Cursor 6} {3440406 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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@ -459,4 +468,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {8561077 ns} {8576725 ns}
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WaveRestoreZoom {0 ns} {12494134 ns}
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@ -67,10 +67,13 @@ module trap (
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assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
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assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
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assign InterruptM = PendingInterruptM & ~CommittedM;
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assign ExceptionM = TrapM;
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//assign ExceptionM = TrapM;
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assign ExceptionM = Exception1M;
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// *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M
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// with no interrupts. However, Ross intended the datacache to use Exception without interrupts, so there is something subtle
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// to sort out here.
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// *** as of 8/13/21, switching to Exception1M does not seem to cause any failures. It's possible the bug was
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// fixed inadvertantly as the dcache was debugged.
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// Trigger Traps and RET
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// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
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@ -311,30 +311,31 @@ module testbench();
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// override on special conditions
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#1;
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if(textW.substr(0,5) == "rdtime") begin
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$display("%t:Releasing force of CSRReadValM.", $time);
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release dut.hart.priv.csr.CSRReadValM;
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//release dut.hart.ieu.dp.regf.wd3;
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end
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%t: releasing force of ReadDataM.", $time);
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release dut.hart.ieu.dp.ReadDataM;
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end
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// remove forces on interrupts
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for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
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if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
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//what type?
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$display("$t: Releasing all forces on interrupts", $time);
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release dut.hart.priv.SwIntM;
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release dut.hart.priv.TimerIntM;
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release dut.hart.priv.ExtIntM;
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if(~dut.hart.StallW) begin
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if(textM.substr(0,5) == "rdtime") begin
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$display("%t:Releasing force of CSRReadValM.", $time);
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release dut.hart.priv.csr.CSRReadValM;
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//release dut.hart.ieu.dp.regf.wd3;
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end
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%t: releasing force of ReadDataM.", $time);
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release dut.hart.ieu.dp.ReadDataM;
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end
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// remove forces on interrupts
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for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
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if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
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//what type?
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$display("%t: Releasing all forces on interrupts", $time);
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release dut.hart.priv.SwIntM;
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release dut.hart.priv.TimerIntM;
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release dut.hart.priv.ExtIntM;
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end
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end
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end
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end
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end
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Block a user