mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
Converted the icache type from logic to state type.
This commit is contained in:
Ross Thompson
parent
b5d6c4fb46
commit
642efbb563
@ -314,8 +314,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadDataBlockWayMaskedM}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
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@ -340,31 +338,29 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM r
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/BlockReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/FetchCount
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
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@ -476,16 +472,10 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HRDATA
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HSIZED
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset0
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset4
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset5
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset6
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset7
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add wave -noupdate /testbench/dut/hart/ExceptionM
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add wave -noupdate /testbench/dut/hart/PendingInterruptM
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add wave -noupdate /testbench/dut/hart/TrapM
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@ -506,4 +496,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {1280 ns} {3534 ns}
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WaveRestoreZoom {0 ns} {325837 ns}
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83
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
83
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
@ -71,51 +71,51 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
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);
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// FSM states
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localparam STATE_READY = 'h0;
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localparam STATE_HIT_SPILL = 'h1; // spill, block 0 hit
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localparam STATE_HIT_SPILL_MISS_FETCH_WDV = 'h2; // block 1 miss, issue read to AHB and wait data.
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localparam STATE_HIT_SPILL_MISS_FETCH_DONE = 'h3; // write data into SRAM/LUT
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localparam STATE_HIT_SPILL_MERGE = 'h4; // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
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typedef enum {STATE_READY,
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STATE_HIT_SPILL, // spill, block 0 hit
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STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
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STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
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STATE_HIT_SPILL_MERGE, // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
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// a challenge is the spill signal gets us out of the ready state and moves us to
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// 1 of the 2 spill branches. However the original fsm design had us return to
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// the ready state when the spill + hits/misses were fully resolved. The problem
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// is the spill signal is based on PCPF so when we return to READY to check if the
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// cache has a hit it still expresses spill. We can fix in 1 of two ways.
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// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
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// to the CPU advancing the CPU and icache to the next instruction.
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// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
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// to the READY state.
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// The first first option is more robust and increases the number of states by 2. The
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// second option is seams like it should work, but I worry there is a hidden interaction
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// between CPU stalling and that register.
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// Picking option 1.
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// a challenge is the spill signal gets us out of the ready state and moves us to
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// 1 of the 2 spill branches. However the original fsm design had us return to
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// the ready state when the spill + hits/misses were fully resolved. The problem
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// is the spill signal is based on PCPF so when we return to READY to check if the
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// cache has a hit it still expresses spill. We can fix in 1 of two ways.
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// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
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// to the CPU advancing the CPU and icache to the next instruction.
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// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
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// to the READY state.
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// The first first option is more robust and increases the number of states by 2. The
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// second option is seams like it should work, but I worry there is a hidden interaction
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// between CPU stalling and that register.
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// Picking option 1.
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localparam STATE_HIT_SPILL_FINAL = 'h5; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
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STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
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STATE_MISS_READ, // read block 1 from SRAM/LUT
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localparam STATE_MISS_FETCH_WDV = 'h6; // aligned miss, issue read to AHB and wait for data.
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localparam STATE_MISS_FETCH_DONE = 'h7; // write data into SRAM/LUT
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localparam STATE_MISS_READ = 'h8; // read block 1 from SRAM/LUT
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STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
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STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
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STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
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STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
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STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.
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STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
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STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
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STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
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localparam STATE_MISS_SPILL_FETCH_WDV = 'h9; // spill, miss on block 0, issue read to AHB and wait
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localparam STATE_MISS_SPILL_FETCH_DONE = 'ha; // write data into SRAM/LUT
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localparam STATE_MISS_SPILL_READ1 = 'hb; // read block 0 from SRAM/LUT
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localparam STATE_MISS_SPILL_2 = 'hc; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_2_START = 'hd; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_MISS_FETCH_WDV = 'he; // miss on block 1, issue read to AHB and wait
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localparam STATE_MISS_SPILL_MISS_FETCH_DONE = 'hf; // write data to SRAM/LUT
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localparam STATE_MISS_SPILL_MERGE = 'h10; // read block 0 of CPU access,
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STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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localparam STATE_MISS_SPILL_FINAL = 'h11; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
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STATE_TLB_MISS,
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STATE_TLB_MISS_DONE
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} statetype;
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localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
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localparam STATE_TLB_MISS = 'h13;
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localparam STATE_TLB_MISS_DONE = 'h14;
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localparam AHBByteLength = `XLEN / 8;
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localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
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@ -129,7 +129,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
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localparam integer PA_WIDTH = `PA_BITS - 2;
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logic [4:0] CurrState, NextState;
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statetype CurrState, NextState;
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logic hit, spill;
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logic SavePC;
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logic [1:0] PCMux;
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@ -187,10 +187,9 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
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// the FSM is always runing, do not stall.
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flopr #(5) stateReg(.clk(clk),
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.reset(reset),
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.d(NextState),
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.q(CurrState));
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always_ff @(posedge clk, posedge reset)
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if (reset) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
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assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
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39
wally-pipelined/src/cache/icache.sv
vendored
39
wally-pipelined/src/cache/icache.sv
vendored
@ -70,15 +70,15 @@ module icache
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ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES))
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cachemem(
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.*,
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// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
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cachemem(.clk,
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.reset,
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.flush(FlushMem),
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.PCTagF,
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.PCNextIndexF,
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.WriteEnable(ICacheMemWriteEnable),
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.WriteLine(ICacheMemWriteData),
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.ReadLineF(ReadLineF),
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.HitF(ICacheMemReadValid)
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);
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.ReadLineF,
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.HitF(ICacheMemReadValid));
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always_comb begin
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case (PCTagF[4:1])
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@ -105,7 +105,32 @@ module icache
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end
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ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*);
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ICacheCntrl #(.BLOCKLEN(BLOCKLEN))
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controller(.clk,
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.reset,
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.StallF,
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.StallD,
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.FlushD,
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.PCNextF,
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.PCPF,
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.ICacheMemReadData,
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.ICacheMemReadValid,
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.PCTagF,
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.PCNextIndexF,
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.ICacheReadEn,
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.ICacheMemWriteEnable,
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.ICacheMemWriteData,
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.CompressedF,
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.FinalInstrRawF,
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.ICacheStallF,
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. EndFetchState,
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.ITLBMissF,
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.ITLBWriteF,
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.WalkerInstrPageFaultF,
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.InstrInF,
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.InstrAckF,
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.InstrPAdrF,
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.InstrReadF);
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// For now, assume no writes to executable memory
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assign FlushMem = 1'b0;
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