Ross Thompson b6e2710f5d Confirmed David's changes to the interrupt code. ... When a timer interrupt occurs it should be routed to the machine interrupt pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is Machine. This is true for all the interrupts. The interrupt should not be masked even though it is delegated to a lower privilege. Since the CPU is currently in machine mode the interrupt must be taken if MIE. Additionally added a new qemu script which pipes together all the parsing and post processing scripts to produce the singular all.txt trace without the massivie intermediate files.		2021-08-22 21:36:31 -05:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
linux-testgen	Confirmed David's changes to the interrupt code.	2021-08-22 21:36:31 -05:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa
regression	Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.	2021-08-19 10:33:11 -05:00
src	Confirmed David's changes to the interrupt code.	2021-08-22 21:36:31 -05:00
testbench	Confirmed David's changes to the interrupt code.	2021-08-22 21:36:31 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00