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Added CommitedM to data cache output.

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This commit is contained in:
Ross Thompson 2021-07-13 22:43:42 -05:00
parent 278bbfbe3c
commit b6e5670bc3
3 changed files with 16 additions and 13 deletions
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20
wally-pipelined/src/cache/dcache.sv vendored
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@ -44,6 +44,7 @@ module dcache
input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataW,
output logic DCacheStall,
output logic CommittedM,
// inputs from TLB and PMA/P
input logic FaultM,
@ -311,12 +312,6 @@ module dcache
typedef enum {STATE_READY,
STATE_READ_MISS_FETCH_WDV,
STATE_READ_MISS_FETCH_DONE,
STATE_READ_MISS_CHECK_EVICTED_DIRTY,
STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK,
STATE_READ_MISS_WRITE_CACHE_BLOCK,
STATE_READ_MISS_READ_WORD,
STATE_MISS_FETCH_WDV,
STATE_MISS_FETCH_DONE,
STATE_MISS_EVICT_DIRTY,
@ -397,7 +392,8 @@ module dcache
AHBRead = 1'b0;
AHBWrite = 1'b0;
SelAMOWrite = 1'b0;
CommittedM = 1'b0;
case (CurrState)
STATE_READY: begin
// TLB Miss
@ -466,6 +462,8 @@ module dcache
PreCntEn = 1'b1;
AHBRead = 1'b1;
SelAdrM = 1'b1;
CommittedM = 1'b1;
if (FetchCountFlag & AHBAck) begin
NextState = STATE_MISS_FETCH_DONE;
end else begin
@ -477,6 +475,7 @@ module dcache
DCacheStall = 1'b1;
SelAdrM = 1'b1;
CntReset = 1'b1;
CommittedM = 1'b1;
if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY;
end else begin
@ -491,11 +490,13 @@ module dcache
SelAdrM = 1'b1;
SetValidM = 1'b1;
ClearDirtyM = 1'b1;
CommittedM = 1'b1;
end
STATE_MISS_READ_WORD: begin
SelAdrM = 1'b1;
DCacheStall = 1'b1;
CommittedM = 1'b1;
if (MemRWM[1]) begin
NextState = STATE_MISS_READ_WORD_DELAY;
// delay state is required as the read signal MemRWM[1] is still high when we
@ -508,6 +509,7 @@ module dcache
STATE_MISS_READ_WORD_DELAY: begin
SelAdrM = 1'b1;
NextState = STATE_READY;
CommittedM = 1'b1;
end
STATE_MISS_WRITE_WORD: begin
@ -516,6 +518,7 @@ module dcache
SelAdrM = 1'b1;
NextState = STATE_READY;
DCacheStall = 1'b0;
CommittedM = 1'b1;
end
STATE_MISS_EVICT_DIRTY: begin
@ -523,6 +526,7 @@ module dcache
PreCntEn = 1'b1;
AHBWrite = 1'b1;
SelAdrM = 1'b1;
CommittedM = 1'b1;
if( FetchCountFlag & AHBAck) begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
end else begin
@ -548,6 +552,7 @@ module dcache
STATE_UNCACHED_WRITE : begin
DCacheStall = 1'b1;
AHBWrite = 1'b1;
CommittedM = 1'b1;
if(AHBAck) begin
NextState = STATE_UNCACHED_WRITE_DONE;
end else begin
@ -556,6 +561,7 @@ module dcache
end
STATE_UNCACHED_WRITE_DONE: begin
CommittedM = 1'b1;
NextState = STATE_READY;
end
default: begin

6
wally-pipelined/src/lsu/lsu.sv
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@ -99,7 +99,9 @@ module lsu
logic DTLBPageFaultM;
logic MemAccessM;
/* -----\/----- EXCLUDED -----\/-----
logic preCommittedM;
-----/\----- EXCLUDED -----/\----- */
typedef enum {STATE_READY,
STATE_FETCH,
@ -135,7 +137,6 @@ module lsu
logic [`XLEN-1:0] MemAdrEtoDCache;
logic [`XLEN-1:0] ReadDataWfromDCache;
logic StallWtoDCache;
logic CommittedMfromDCache;
logic SquashSCWfromDCache;
logic DataMisalignedMfromDCache;
logic HPTWReady;
@ -187,7 +188,6 @@ module lsu
.MemAdrM(MemAdrM),
.StallW(StallW),
.ReadDataW(ReadDataW),
.CommittedM(CommittedM),
.SquashSCW(SquashSCW),
.DataMisalignedM(DataMisalignedM),
.LSUStall(LSUStall),
@ -198,7 +198,6 @@ module lsu
.AtomicMtoDCache(AtomicMtoDCache),
.MemAdrMtoDCache(MemAdrMtoDCache),
.StallWtoDCache(StallWtoDCache),
.CommittedMfromDCache(CommittedMfromDCache),
.SquashSCWfromDCache(SquashSCWfromDCache),
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
.ReadDataWfromDCache(ReadDataWfromDCache),
@ -319,6 +318,7 @@ module lsu
.WriteDataM(WriteDataM),
.ReadDataW(ReadDataWfromDCache),
.DCacheStall(DCacheStall),
.CommittedM(CommittedM),
.FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults.
.DTLBMissM(DTLBMissM),
.CacheableM(CacheableM),

3
wally-pipelined/src/lsu/lsuArb.sv
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@ -45,7 +45,6 @@ module lsuArb
input logic StallW,
// to CPU
output logic [`XLEN-1:0] ReadDataW,
output logic CommittedM,
output logic SquashSCW,
output logic DataMisalignedM,
output logic LSUStall,
@ -58,7 +57,6 @@ module lsuArb
output logic [`XLEN-1:0] MemAdrMtoDCache,
output logic StallWtoDCache,
// from LSU
input logic CommittedMfromDCache,
input logic SquashSCWfromDCache,
input logic DataMisalignedMfromDCache,
input logic [`XLEN-1:0] ReadDataWfromDCache,
@ -149,7 +147,6 @@ module lsuArb
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux
assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux
assign CommittedM = SelPTW ? 1'b0 : CommittedMfromDCache;
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
// *** need to rename DcacheStall and Datastall.