Renamed DCacheStall to LSUStall in hart and hazard.

Added missing logic in lsu.

wally-pipelined/src/cache/dcache.sv

@@ -433,7 +433,7 @@ module dcache
     case (CurrState)
       STATE_READY: begin
 	// TLB Miss	
-	if(AnyCPUReqM & DTLBMissM) begin                      
+	if(AnyCPUReqM & DTLBMissM) begin  
 	  NextState = STATE_PTW_READY;
 	end
 	// amo hit

wally-pipelined/src/hazard/hazard.sv

@@ -31,7 +31,7 @@ module hazard(
   // Detect hazards
 	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
 	      input logic  LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
-	      input logic  DCacheStall, ICacheStallF,
+	      input logic  LSUStall, ICacheStallF,
               input logic  FPUStallD, FStallD,
 	      input logic  DivBusyE,FDivBusyE,
   // Stall & flush outputs
@@ -59,7 +59,7 @@ module hazard(
   assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);    // stall in decode if instruction is a load/mul/csr dependent on previous
   assign StallECause = DivBusyE | FDivBusyE;
   assign StallMCause = 0; 
-  assign StallWCause = DCacheStall | ICacheStallF;
+  assign StallWCause = LSUStall | ICacheStallF;
 
   assign StallF = StallFCause | StallD;
   assign StallD = StallDCause | StallE;

wally-pipelined/src/lsu/lsu.sv

@@ -152,6 +152,7 @@ module lsu
 
   logic 		       CommittedMfromDCache;
   logic 		       PendingInterruptMtoDCache;
+  logic 		       FlushWtoDCache;
   
   
   pagetablewalker pagetablewalker(

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -126,7 +126,7 @@ module wallypipelinedhart
 
   // IMem stalls
   logic 		    ICacheStallF;
-  logic 		    DCacheStall;
+  logic 		    LSUStall;
 
   
 
@@ -233,7 +233,7 @@ module wallypipelinedhart
 
 	  .DTLBHitM(DTLBHitM), // not connected remove
 
-	  .LSUStall(DCacheStall));                     // change to DCacheStall
+	  .LSUStall(LSUStall));                     // change to LSUStall