cvw/wally-pipelined
2021-08-25 06:46:41 -04:00
..
bin
config move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
linux-testgen Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. 2021-08-05 16:49:03 -05:00
misc
ppa
regression Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
src simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
testbench Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
testgen
lint-wally