bbracker 8cbd83e804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-07-19 13:21:04 -04:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Added FLEN, NE, NF to config and started using these in FMA1	2021-07-18 17:28:25 -04:00
linux-testgen	change memread testvectors to not left-shift bytes and half-words	2021-07-18 21:49:53 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	change buildroot expectations to match reality	2021-07-19 13:20:53 -04:00
src	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00
testbench	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00