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https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
simplified or_rows generation and renamed oneHotDecoder to onehotdecoder
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8
wally-pipelined/src/cache/cacheLRU.sv
vendored
8
wally-pipelined/src/cache/cacheLRU.sv
vendored
@ -67,8 +67,8 @@ module cacheLRU
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assign EncVicWay[1] = LRUIn[2];
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assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
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oneHotDecoder #(2)
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oneHotDecoder(.bin(EncVicWay),
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onehotdecoder #(2)
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waydec(.bin(EncVicWay),
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.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
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end else if (NUMWAYS == 8) begin : EightWay
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@ -100,8 +100,8 @@ module cacheLRU
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LRUIn[2] ? LRUIn[1] : LRUIn[0];
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oneHotDecoder #(3)
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oneHotDecoder(.bin(EncVicWay),
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onehotdecoder #(3)
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waydec(.bin(EncVicWay),
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.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
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VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
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end
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4
wally-pipelined/src/cache/dcache.sv
vendored
4
wally-pipelined/src/cache/dcache.sv
vendored
@ -197,8 +197,8 @@ module dcache
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.y(SRAMAdr));
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oneHotDecoder #(LOGWPL)
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oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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onehotdecoder #(LOGWPL)
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adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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.decoded(MemPAdrDecodedW));
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@ -25,7 +25,7 @@
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`include "wally-config.vh"
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module oneHotDecoder
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module onehotdecoder
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#(parameter WIDTH = 2)
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(input logic [WIDTH-1:0] bin,
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output logic [2**WIDTH-1:0] decoded
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@ -36,12 +36,19 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
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logic [COLS-1:0] mid[ROWS-1:0];
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genvar row, col;
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generate
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assign mid[1] = a[0] | a[1];
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for (row=2; row < ROWS; row++)
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assign mid[row] = mid[row-1] | a[row];
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assign y = mid[ROWS-1];
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/*
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for (col = 0; col < COLS; col++) begin
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assign mid[1][col] = a[0][col] | a[1][col];
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for (row=2; row < ROWS; row++)
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assign mid[row][col] = mid[row-1][col] | a[row][col];
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assign y[col] = mid[ROWS-1][col];
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end
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*/
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endgenerate
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endmodule
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