simplified or_rows generation and renamed oneHotDecoder to onehotdecoder

This commit is contained in:
David Harris 2021-08-25 06:46:41 -04:00
parent 696be3ff68
commit cf1e458ccf
4 changed files with 14 additions and 7 deletions

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@ -67,8 +67,8 @@ module cacheLRU
assign EncVicWay[1] = LRUIn[2];
assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
oneHotDecoder #(2)
oneHotDecoder(.bin(EncVicWay),
onehotdecoder #(2)
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
end else if (NUMWAYS == 8) begin : EightWay
@ -100,8 +100,8 @@ module cacheLRU
LRUIn[2] ? LRUIn[1] : LRUIn[0];
oneHotDecoder #(3)
oneHotDecoder(.bin(EncVicWay),
onehotdecoder #(3)
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end

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@ -197,8 +197,8 @@ module dcache
.y(SRAMAdr));
oneHotDecoder #(LOGWPL)
oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
onehotdecoder #(LOGWPL)
adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecodedW));

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@ -25,7 +25,7 @@
`include "wally-config.vh"
module oneHotDecoder
module onehotdecoder
#(parameter WIDTH = 2)
(input logic [WIDTH-1:0] bin,
output logic [2**WIDTH-1:0] decoded

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@ -36,12 +36,19 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
logic [COLS-1:0] mid[ROWS-1:0];
genvar row, col;
generate
assign mid[1] = a[0] | a[1];
for (row=2; row < ROWS; row++)
assign mid[row] = mid[row-1] | a[row];
assign y = mid[ROWS-1];
/*
for (col = 0; col < COLS; col++) begin
assign mid[1][col] = a[0][col] | a[1][col];
for (row=2; row < ROWS; row++)
assign mid[row][col] = mid[row-1][col] | a[row][col];
assign y[col] = mid[ROWS-1][col];
end
*/
endgenerate
endmodule