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hptw: Simplified TranslationVAdr calculation based just on DTLBWalk

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This commit is contained in:
David Harris 2021-07-17 14:16:33 -04:00
parent af02437c3a
commit ad44835e6e
1 changed files with 3 additions and 6 deletions
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9
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -80,6 +80,7 @@ module pagetablewalker
logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE;
logic StartWalk;
logic EndWalk;
logic PRegEn;
logic [1:0] NextPageType;
typedef enum {LEVEL0_SET_ADR, LEVEL0_WDV, LEVEL0,
@ -90,18 +91,14 @@ module pagetablewalker
statetype WalkerState, NextWalkerState, InitialWalkerState;
logic PRegEn;
logic SelDataTranslation;
logic [`SVMODE_BITS-1:0] SvMode;
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign MemWrite = MemRWM[0];
// Prefer data address translations over instruction address translations
assign SelDataTranslation = DTLBWalk | DTLBMissM; // *** missM is probably unnecessary
assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
// Determine which address to translate
assign TranslationVAdr = DTLBWalk ? MemAdrM : PCF;
flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
flopenrc #(1) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, DTLBMissM, DTLBWalk);