Kevin Kim
19f0cf7a35
putting back tests in tests vh
2024-06-21 21:51:44 -07:00
Kevin Kim
00bf3faa9c
changed intdivb width
2024-06-21 21:31:19 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS
2024-06-21 15:17:59 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Rose Thompson
e1fc44a5bf
Merge pull request #849 from davidharrishmc/dev
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lint cleanup and divider optimization
2024-06-20 09:04:19 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main
...
Update riscv-arch-test
2024-06-20 08:43:41 -07:00
Jordan Carlin
90f5a4ef48
Only run fmsub_b15 for f_fma test
2024-06-20 07:48:33 -07:00
David Harris
25780f53ce
Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.
2024-06-20 00:57:58 -07:00
Ross Thompson
d368f2e77e
Removed *** from testbench.
2024-06-19 13:51:37 -07:00
Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
Jordan Carlin
156bfc0387
Update f_fma tests to use smaller files from riscv-arch-test
2024-06-18 23:38:03 -07:00
Jordan Carlin
d58b454a8b
Finish switching Zfa to use riscv-arch-test
2024-06-18 23:31:37 -07:00
Jordan Carlin
955f5d831f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-18 22:39:05 -07:00
David Harris
ecae1100f6
Lint cleanup
2024-06-18 05:49:49 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
312c9c9f55
Updated logger to new IClass signal name
2024-06-12 07:24:05 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Jordan Carlin
c560a0ae8f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-01 23:22:30 -07:00
Rose Thompson
48fd365b9d
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
...
testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Jordan Carlin
6f79dca9c4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-27 12:29:24 -07:00
Jordan Carlin
dcafe4793e
Add froundnx and fround.d tests
2024-05-24 15:16:35 -07:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Jordan Carlin
f410bbb79e
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
2024-05-21 00:04:27 -07:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
0ed75a3ff5
Reverted testbench-imperas.sv incase someone wants this.
2024-05-17 16:48:29 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
...
The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
e6902eb4d2
Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
2024-05-17 16:08:14 -05:00
Rose Thompson
d9807bb909
This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
2024-05-17 14:45:37 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
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Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
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Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
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- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
d4ac53f000
commented legal TEST options
2024-05-13 07:22:30 -07:00
David Harris
75c10bddfa
Moved case.sh to tests/fp
2024-05-13 07:12:16 -07:00
David Harris
d0dad1d9f6
Fixed testbench_fp to use modified unpacker
2024-05-12 12:11:48 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
David Harris
c0743a1fcf
Added missing convert F to/from Int64 tests for arch64f
2024-05-11 02:29:47 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df
Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1.
2024-05-10 08:51:59 -05:00
David Harris
66b33c09be
Added Zaamo and Zalrsc support to testbench and regression
2024-05-10 05:41:00 -07:00
David Harris
54750ae4d5
Fixed out-of-bound vector accesses in testbench_fp when FLEN < Q_LEN
2024-05-09 19:52:37 -07:00
David Harris
bdd0043cd1
Testbench terminates buildroot sim at instruction limit
2024-05-09 07:58:53 -07:00
David Harris
47af54b131
Fixed buildroot prematurely terminating in VCS
2024-05-09 07:29:45 -07:00
David Harris
0d1d59a3d8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-08 18:58:01 -07:00
Divya2030
31ae18922b
regression_wally vcs run works
2024-05-08 04:25:03 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
Divya2030
a3f1a274d2
VCS Simulation Passed
2024-05-07 10:41:02 -07:00
David Harris
06d3591a15
Divy's change for VCS signature checking
2024-05-04 02:45:43 -07:00
Divya2030
12a9c0ebd6
pmp coverage
2024-05-02 11:53:32 -07:00
Divya2030
ee566aa856
pmp coverage
2024-05-02 11:53:04 -07:00
Divya2030
7a5eac963e
Revert "pmp functional coverage basic"
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This reverts commit db2b07b05d
2024-05-02 11:43:33 -07:00
Divya2030
3853f94337
Revert "initial commit pmp basic coverage working"
...
This reverts commit 7ca1c976c0
2024-05-02 11:23:59 -07:00
Divya2030
9f27f3fe28
Merge branch 'main' of github.com:Divya2030/cvw
2024-05-02 11:21:05 -07:00
Divya2030
db2b07b05d
pmp functional coverage basic
2024-05-02 11:20:03 -07:00
Divya2030
694c69c651
Merge branch 'openhwgroup:main' into main
2024-05-02 10:34:15 -07:00
Divya2030
7ca1c976c0
initial commit pmp basic coverage working
2024-05-02 10:33:29 -07:00
David Harris
e667adf946
Added covergen directed coverage generator
2024-05-01 14:47:37 -07:00
David Harris
9b22275438
Removed unused signals from WallyTracer
2024-04-30 08:54:28 -07:00
David Harris
fc7c183d56
Added fcvtmod.w.d_b22 to regression now that it works in Sail
2024-04-29 17:52:21 -07:00
David Harris
160c11d786
Integrating riscv-dv coverage
2024-04-24 10:17:49 -07:00
David Harris
6415bfc3c2
Code and testbench cleanup
2024-04-23 10:17:44 -07:00
David Harris
f9eec8c43f
Merged wsim changes
2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493
Add support for dumping vcd.
2024-04-22 13:03:51 -07:00
David Harris
26711083df
Flushing uart.out file to observe progress
2024-04-21 20:08:35 -07:00
David Harris
03f49dea3f
regression printing improvements
2024-04-21 19:45:09 -07:00
David Harris
be15a11622
Fixed conflicts on getenv
2024-04-21 08:38:13 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
1817ab2e11
testbench import is happy now for Questa, but throws lint warning for VCS
2024-04-20 23:13:13 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
338f37b570
Moved getenv/getenvval declaration to config-shared so lint and regression both run
2024-04-20 17:19:42 -07:00
David Harris
571b67f565
Merging PR738
2024-04-20 17:15:17 -07:00
slmnemo
f0229e970b
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
2024-04-20 17:07:54 -07:00
slmnemo
66a002d879
Removed unused rmCmd string declaration
2024-04-20 16:58:23 -07:00
slmnemo
354d447269
Changed testbench to use fopen instead of opening and closing uartfile whenever writing
2024-04-20 16:56:54 -07:00
David Harris
d9ebfdfc4f
Enabled Zcb tests
2024-04-20 13:16:54 -07:00
Quswar Abid
1b18568d87
the fix Rose provided in meeting
2024-04-17 09:39:21 -07:00
Kunlin Han
29c19d9cb4
Add system function through DPI to avoid missing support in Verilator.
2024-04-16 11:23:00 -07:00
Rose Thompson
1eb1beed95
Fixed merge conflict bug in the last pull request.
2024-04-16 10:32:24 -05:00
Rose Thompson
9fe86712d8
Merge branch 'main' into wsim_verilator
2024-04-16 09:07:50 -05:00
David Harris
160162c98a
Merge pull request #728 from Karl-Han/verilator_getenv
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Add support for getenvval as wrapper for Verilator's getenv
2024-04-15 17:55:34 -06:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
slmnemo
342c99d6ea
Rearranged uart_logger block to only generate if UART is supported
2024-04-12 21:30:33 -07:00
Kunlin Han
eeb5c59143
Remove unnecessary sig and avoid uninitialized signal inside always block.
2024-04-12 16:06:10 -07:00
Kunlin Han
4d9de94029
Add support for getenvval as wrapper for Verilator's getenv.
2024-04-12 14:59:04 -07:00
David Harris
60e70c1986
Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.
2024-04-08 05:57:18 -07:00
David Harris
d182a2925e
Fixed bug in testbench_fp for XLEN > FLEN
2024-04-07 05:40:18 -07:00
Rose Thompson
bb072fba84
Fixed the buildroot issue.
2024-04-06 18:25:53 -05:00
Rose Thompson
46fdfde7ec
Removed unnecessary display from testbench.
2024-04-06 16:10:18 -05:00
Rose Thompson
8885c32f7c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-04-06 15:55:00 -05:00
David Harris
e8111da88a
Removed unused old regression-wally
2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e
Added GUI support and removed unused wave files
2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90
Passing arguments to buildroot, not yet checking result correctly
2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f
Working on buildroot in regression
2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
David Harris
9ee7544d3c
TestFloat running; normal testbench broken
2024-04-06 09:28:07 -07:00
David Harris
4b19f6d542
testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./
2024-04-06 08:22:39 -07:00
slmnemo
d107a42e8c
Replaced rewrite command with system rm command for uart file. Fixed comment on line 573
2024-04-05 21:39:41 -07:00
slmnemo
2fcae601a9
Replaced funky rewrite call with file removal
2024-04-05 20:59:08 -07:00
David Harris
7b56809323
wsim runs a Questa sim
2024-04-05 19:08:14 -07:00
slmnemo
3ee25c8936
Merged testbench changes
2024-04-05 17:20:03 -07:00
slmnemo
5378b61eb2
Added UART output file buildroot_uart.out for Linux test 'buildroot'.
2024-04-05 17:18:03 -07:00
Rose Thompson
23e51e7277
starting on functional coverage for fence.i.
2024-04-04 15:44:57 -05:00
David Harris
ccd0e9cd0c
Clean up testbench-fp for Verilator
2024-04-03 17:26:41 -07:00
David Harris
ae8d581f4e
Started implementing Verilator for testfloat
2024-04-03 17:09:19 -07:00
Divya2030
aa6eacbce5
Merge branch 'openhwgroup:main' into main
2024-04-03 10:40:30 -07:00
Divya2030
135f3b6f8f
vcs testbench
2024-04-03 10:39:02 -07:00
David Harris
8755966f50
Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved
2024-04-03 07:23:02 -07:00
David Harris
8741b01818
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-03 06:51:24 -07:00
David Harris
929eb0430c
Testbench uses posedge control signals to speed up Verilator
2024-04-03 06:51:18 -07:00
Rose Thompson
c11d7ea55e
Fixed bug in the testbench which did not allow external memory to work correctly.
2024-04-01 10:59:40 -05:00
Rose Thompson
4a7c16990f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-28 13:45:12 -05:00
Rose Thompson
35eba468f7
Removed unused testbench-xcelium.sv.
2024-03-28 13:43:26 -05:00
Rose Thompson
b87cdd49a3
Merge pull request #690 from davidharrishmc/dev
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fcvt.h.l fixes, removed delays
2024-03-28 13:42:41 -05:00
Rose Thompson
081cf5be55
Fixed the CacheHit logger bug.
2024-03-28 13:40:01 -05:00
David Harris
4eb7de7381
Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test
2024-03-26 13:58:59 -07:00
David Harris
0caab3c0c9
Removed delays from cacheLRU and testbench
2024-03-25 12:20:25 -07:00
David Harris
690338b758
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
2024-03-25 06:08:27 -07:00
Jordan Carlin
d580d7af5d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-23 17:56:23 -07:00
Jordan Carlin
fd97108dc3
Update testbench-fp to support Zfa in FPU modules
2024-03-23 17:55:59 -07:00
David Harris
bae52cf13d
Merge pull request #678 from Karl-Han/latest
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[Resolved Conflict] Remove all #delay from non-testbench
2024-03-23 15:18:04 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
David Harris
b4a914a6e3
Commented out fcvt.h.l tests that don't run on fh_arch64gc arch64zfh; added testbench feature to print when the program jumps to address 0, presumably a bad trap handler
2024-03-14 21:53:30 -07:00
David Harris
9ff9f9e0ae
Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
2024-03-14 19:03:57 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
9a1fdba077
Added more Zbkb tests shared with Zbb
2024-03-10 22:24:16 -07:00
David Harris
2580d37fc0
ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder
2024-03-10 22:03:57 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
Rose Thompson
e870e8137b
Finished Wally rvvi tracer.
2024-03-08 09:16:30 -06:00
Rose Thompson
24dffa39d5
Yay. David and I got our first Quad load/store instructions working!
2024-03-07 12:48:52 -06:00
