slmnemo 354d447269 Changed testbench to use fopen instead of opening and closing uartfile whenever writing		2024-04-20 16:56:54 -07:00
..
common	Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test	2024-04-06 10:34:21 -07:00
coverage	starting on functional coverage for fence.i.	2024-04-04 15:44:57 -05:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Remove all #delay from non-testbench.	2024-03-16 11:20:32 -07:00
testbench_fp.sv	Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.	2024-04-08 05:57:18 -07:00
testbench-imperas.sv	the fix Rose provided in meeting	2024-04-17 09:39:21 -07:00
testbench.sv	Changed testbench to use fopen instead of opening and closing uartfile whenever writing	2024-04-20 16:56:54 -07:00
tests_fp.vh	testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./	2024-04-06 08:22:39 -07:00
tests.vh	wsim runs a Questa sim	2024-04-05 19:08:14 -07:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00