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Yay. David and I got our first Quad load/store instructions working!

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This commit is contained in:
Rose Thompson 2024-03-07 12:48:52 -06:00
parent eea235a3c3
commit 24dffa39d5
3 changed files with 7 additions and 2 deletions
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1
testbench/testbench.sv
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@ -124,6 +124,7 @@ module testbench;
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
"wally64q": if (P.Q_SUPPORTED) tests = wally64q;
"wally64a": if (P.A_SUPPORTED) tests = wally64a;
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;

4
testbench/tests.vh
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@ -869,6 +869,10 @@ string imperas32f[] = '{
"rv32i_m/I/XORI-01"
};
string wally64q[] = '{
`WALLYTEST,
"rv64i_m/Q/src/WALLY-q-01.S"
};
string wally64a[] = '{
`WALLYTEST,

4
tests/riscof/spike/spike_rv64gc_isa.yaml
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@ -2,12 +2,12 @@ hart_ids: [0]
hart0:
# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x800000000014112D
reset-val: 0x800000000015112D
rv32:
accessible: false
rv64: