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Finished Wally rvvi tracer.

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This commit is contained in:
Rose Thompson 2024-03-08 09:16:30 -06:00
parent 402d71e5f4
commit e870e8137b
1 changed files with 4 additions and 3 deletions
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7
testbench/common/wallyTracer.sv
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@ -63,7 +63,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic CSRWriteM, CSRWriteW;
logic [11:0] CSRAdrM, CSRAdrW;
logic wfiM;
logic InterruptM;
logic InterruptM, InterruptW;
assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
@ -266,6 +266,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
// **** remove? are these used?
@ -287,9 +288,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order
assign rvvi.insn[0][0] = InstrRawW;
assign rvvi.pc_rdata[0][0] = PCW;
assign rvvi.trap[0][0] = 0;
assign rvvi.trap[0][0] = TrapW;
assign rvvi.halt[0][0] = HaltW;
assign rvvi.intr[0][0] = 0;
assign rvvi.intr[0][0] = InterruptW;
assign rvvi.mode[0][0] = PrivilegeModeW;
assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;