mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
This commit is contained in:
David Harris
parent
fc158689ad
commit
690338b758
@ -1425,10 +1425,10 @@ string imperas32f[] = '{
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"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
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"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
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"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support
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// "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
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"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
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"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:09:38 2023 GMT
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// timestamp : Mon Mar 25 04:42:12 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup.
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,49 +29,49 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
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RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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RVTEST_SIGBASE(x1,signature_x1_1)
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inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
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inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
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val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x3, 0*8, x4, x1, x2,ld)
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inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
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inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
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val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f30, x30, dyn, 0, 0, x3, 1*8, x4, x1, x2,ld)
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inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0 and rm_val == 7
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inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x29; dest:f29; op1val:-0x1; valaddr_reg:x3;
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val_offset:2*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f29, x29, dyn, 0, 0, x3, 2*8, x4, x1, x2,ld)
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inst_3:// rs1==x28, rd==f28,rs1_val == 9223372036854775807 and fcsr == 0 and rm_val == 7
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inst_3:// rs1==x28, rd==f28,rs1_val == 9223372036854775807 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x28; dest:f28; op1val:0x7fffffffffffffff; valaddr_reg:x3;
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val_offset:3*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f28, x28, dyn, 0, 0, x3, 3*8, x4, x1, x2,ld)
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inst_4:// rs1==x27, rd==f27,rs1_val == -9223372036854775807 and fcsr == 0 and rm_val == 7
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inst_4:// rs1==x27, rd==f27,rs1_val == -9223372036854775807 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x27; dest:f27; op1val:-0x7fffffffffffffff; valaddr_reg:x3;
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val_offset:4*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f27, x27, dyn, 0, 0, x3, 4*8, x4, x1, x2,ld)
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inst_5:// rs1==x26, rd==f26,rs1_val == 5270258713649211392 and fcsr == 0 and rm_val == 7
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inst_5:// rs1==x26, rd==f26,rs1_val == 5270258713649211392 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x26; dest:f26; op1val:0x4923b8608577e800; valaddr_reg:x3;
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val_offset:5*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f26, x26, dyn, 0, 0, x3, 5*8, x4, x1, x2,ld)
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inst_6:// rs1==x25, rd==f25,rs1_val == -5270258713649211392 and fcsr == 0 and rm_val == 7
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inst_6:// rs1==x25, rd==f25,rs1_val == -5270258713649211392 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x25; dest:f25; op1val:-0x4923b8608577e800; valaddr_reg:x3;
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val_offset:6*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:09:38 2023 GMT
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// timestamp : Mon Mar 25 04:42:12 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup.
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,399 +29,399 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26)
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RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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RVTEST_SIGBASE(x1,signature_x1_1)
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inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
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inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
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val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x3, 0*8, x4, x1, x2,ld)
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inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
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inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
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val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f30, x30, dyn, 0, 0, x3, 1*8, x4, x1, x2,ld)
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inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
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inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
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val_offset:2*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f29, x29, dyn, 0, 0, x3, 2*8, x4, x1, x2,ld)
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inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
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inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
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val_offset:3*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f28, x28, dyn, 0, 0, x3, 3*8, x4, x1, x2,ld)
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inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
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inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
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val_offset:4*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f27, x27, dyn, 0, 0, x3, 4*8, x4, x1, x2,ld)
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inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
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inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
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val_offset:5*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f26, x26, dyn, 0, 0, x3, 5*8, x4, x1, x2,ld)
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inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
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inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
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val_offset:6*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f25, x25, dyn, 0, 0, x3, 6*8, x4, x1, x2,ld)
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inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
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inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
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val_offset:7*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f24, x24, dyn, 0, 0, x3, 7*8, x4, x1, x2,ld)
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inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
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inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
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val_offset:8*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f23, x23, dyn, 0, 0, x3, 8*8, x4, x1, x2,ld)
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inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
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inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
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val_offset:9*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f22, x22, dyn, 0, 0, x3, 9*8, x4, x1, x2,ld)
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inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
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inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
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val_offset:10*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f21, x21, dyn, 0, 0, x3, 10*8, x4, x1, x2,ld)
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inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
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inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
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val_offset:11*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f20, x20, dyn, 0, 0, x3, 11*8, x4, x1, x2,ld)
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inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
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inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
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val_offset:12*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f19, x19, dyn, 0, 0, x3, 12*8, x4, x1, x2,ld)
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inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
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inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
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val_offset:13*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f18, x18, dyn, 0, 0, x3, 13*8, x4, x1, x2,ld)
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inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
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inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
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val_offset:14*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f17, x17, dyn, 0, 0, x3, 14*8, x4, x1, x2,ld)
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inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
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inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
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val_offset:15*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f16, x16, dyn, 0, 0, x3, 15*8, x4, x1, x2,ld)
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inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
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inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
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/* opcode: fcvt.h.l ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
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val_offset:16*8; rmval:dyn; correctval:??; testreg:x2;
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fcsr_val: 0*/
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TEST_FPIO_OP(fcvt.h.l, f15, x15, dyn, 0, 0, x3, 16*8, x4, x1, x2,ld)
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inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f14, x14, dyn, 0, 0, x3, 17*8, x4, x1, x2,ld)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f13, x13, dyn, 0, 0, x3, 18*8, x4, x1, x2,ld)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f12, x12, dyn, 0, 0, x3, 19*8, x4, x1, x2,ld)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f11, x11, dyn, 0, 0, x3, 20*8, x4, x1, x2,ld)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f10, x10, dyn, 0, 0, x3, 21*8, x4, x1, x2,ld)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f9, x9, dyn, 0, 0, x3, 22*8, x4, x1, x2,ld)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f8, x8, dyn, 0, 0, x3, 23*8, x4, x1, x2,ld)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f7, x7, dyn, 0, 0, x8, 0*8, x9, x1, x2,ld)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f6, x6, dyn, 0, 0, x8, 1*8, x9, x1, x2,ld)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f5, x5, dyn, 0, 0, x8, 2*8, x9, x1, x6,ld)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f4, x4, dyn, 0, 0, x8, 3*8, x9, x5, x6,ld)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f3, x3, dyn, 0, 0, x8, 4*8, x9, x5, x6,ld)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f2, x2, dyn, 0, 0, x8, 5*8, x9, x5, x6,ld)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f1, x1, dyn, 0, 0, x8, 6*8, x9, x5, x6,ld)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f0, x0, dyn, 0, 0, x8, 7*8, x9, x5, x6,ld)
|
||||
|
||||
inst_32:// rs1_val == 4035756470 and fcsr == 0 and rm_val == 7
|
||||
inst_32:// rs1_val == 4035756470 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xf08cc1b6; valaddr_reg:x8;
|
||||
val_offset:8*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 8*8, x9, x5, x6,ld)
|
||||
|
||||
inst_33:// rs1_val == 6929185936 and fcsr == 0 and rm_val == 7
|
||||
inst_33:// rs1_val == 6929185936 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x19d02fc90; valaddr_reg:x8;
|
||||
val_offset:9*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 9*8, x9, x5, x6,ld)
|
||||
|
||||
inst_34:// rs1_val == 8607351303 and fcsr == 0 and rm_val == 7
|
||||
inst_34:// rs1_val == 8607351303 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x20109c207; valaddr_reg:x8;
|
||||
val_offset:10*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 10*8, x9, x5, x6,ld)
|
||||
|
||||
inst_35:// rs1_val == 22050244097 and fcsr == 0 and rm_val == 7
|
||||
inst_35:// rs1_val == 22050244097 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x5224c0601; valaddr_reg:x8;
|
||||
val_offset:11*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 11*8, x9, x5, x6,ld)
|
||||
|
||||
inst_36:// rs1_val == 51102363774 and fcsr == 0 and rm_val == 7
|
||||
inst_36:// rs1_val == 51102363774 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xbe5f0307e; valaddr_reg:x8;
|
||||
val_offset:12*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 12*8, x9, x5, x6,ld)
|
||||
|
||||
inst_37:// rs1_val == 131206879410 and fcsr == 0 and rm_val == 7
|
||||
inst_37:// rs1_val == 131206879410 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x1e8c8a18b2; valaddr_reg:x8;
|
||||
val_offset:13*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 13*8, x9, x5, x6,ld)
|
||||
|
||||
inst_38:// rs1_val == 268160711063 and fcsr == 0 and rm_val == 7
|
||||
inst_38:// rs1_val == 268160711063 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x3e6f9fb997; valaddr_reg:x8;
|
||||
val_offset:14*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 14*8, x9, x5, x6,ld)
|
||||
|
||||
inst_39:// rs1_val == 453482173015 and fcsr == 0 and rm_val == 7
|
||||
inst_39:// rs1_val == 453482173015 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x6995a4d257; valaddr_reg:x8;
|
||||
val_offset:15*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 15*8, x9, x5, x6,ld)
|
||||
|
||||
inst_40:// rs1_val == 813522083007 and fcsr == 0 and rm_val == 7
|
||||
inst_40:// rs1_val == 813522083007 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xbd69b1dcbf; valaddr_reg:x8;
|
||||
val_offset:16*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 16*8, x9, x5, x6,ld)
|
||||
|
||||
inst_41:// rs1_val == 1168389695644 and fcsr == 0 and rm_val == 7
|
||||
inst_41:// rs1_val == 1168389695644 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x1100973e89c; valaddr_reg:x8;
|
||||
val_offset:17*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 17*8, x9, x5, x6,ld)
|
||||
|
||||
inst_42:// rs1_val == 3524006078498 and fcsr == 0 and rm_val == 7
|
||||
inst_42:// rs1_val == 3524006078498 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x3347f216822; valaddr_reg:x8;
|
||||
val_offset:18*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 18*8, x9, x5, x6,ld)
|
||||
|
||||
inst_43:// rs1_val == 5032232323694 and fcsr == 0 and rm_val == 7
|
||||
inst_43:// rs1_val == 5032232323694 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x493a86b8a6e; valaddr_reg:x8;
|
||||
val_offset:19*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 19*8, x9, x5, x6,ld)
|
||||
|
||||
inst_44:// rs1_val == 10221399934292 and fcsr == 0 and rm_val == 7
|
||||
inst_44:// rs1_val == 10221399934292 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x94bdae98554; valaddr_reg:x8;
|
||||
val_offset:20*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 20*8, x9, x5, x6,ld)
|
||||
|
||||
inst_45:// rs1_val == 31117680965175 and fcsr == 0 and rm_val == 7
|
||||
inst_45:// rs1_val == 31117680965175 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x1c4d2651f637; valaddr_reg:x8;
|
||||
val_offset:21*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 21*8, x9, x5, x6,ld)
|
||||
|
||||
inst_46:// rs1_val == 45718214482007 and fcsr == 0 and rm_val == 7
|
||||
inst_46:// rs1_val == 45718214482007 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x299499ef1857; valaddr_reg:x8;
|
||||
val_offset:22*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 22*8, x9, x5, x6,ld)
|
||||
|
||||
inst_47:// rs1_val == 132508745935081 and fcsr == 0 and rm_val == 7
|
||||
inst_47:// rs1_val == 132508745935081 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x788418bb28e9; valaddr_reg:x8;
|
||||
val_offset:23*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 23*8, x9, x5, x6,ld)
|
||||
|
||||
inst_48:// rs1_val == 194479587133174 and fcsr == 0 and rm_val == 7
|
||||
inst_48:// rs1_val == 194479587133174 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xb0e0ceb506f6; valaddr_reg:x8;
|
||||
val_offset:24*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 24*8, x9, x5, x6,ld)
|
||||
|
||||
inst_49:// rs1_val == 477767642386861 and fcsr == 0 and rm_val == 7
|
||||
inst_49:// rs1_val == 477767642386861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x1b286f29c11ad; valaddr_reg:x8;
|
||||
val_offset:25*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 25*8, x9, x5, x6,ld)
|
||||
|
||||
inst_50:// rs1_val == 1064659746632576 and fcsr == 0 and rm_val == 7
|
||||
inst_50:// rs1_val == 1064659746632576 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x3c84d6a013380; valaddr_reg:x8;
|
||||
val_offset:26*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 26*8, x9, x5, x6,ld)
|
||||
|
||||
inst_51:// rs1_val == 1449063015970349 and fcsr == 0 and rm_val == 7
|
||||
inst_51:// rs1_val == 1449063015970349 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x525ea4652f62d; valaddr_reg:x8;
|
||||
val_offset:27*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 27*8, x9, x5, x6,ld)
|
||||
|
||||
inst_52:// rs1_val == 3454382579804098 and fcsr == 0 and rm_val == 7
|
||||
inst_52:// rs1_val == 3454382579804098 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xc45be1e9667c2; valaddr_reg:x8;
|
||||
val_offset:28*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 28*8, x9, x5, x6,ld)
|
||||
|
||||
inst_53:// rs1_val == 7228908657904184 and fcsr == 0 and rm_val == 7
|
||||
inst_53:// rs1_val == 7228908657904184 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x19aea774ab0a38; valaddr_reg:x8;
|
||||
val_offset:29*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 29*8, x9, x5, x6,ld)
|
||||
|
||||
inst_54:// rs1_val == 12147253371253868 and fcsr == 0 and rm_val == 7
|
||||
inst_54:// rs1_val == 12147253371253868 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x2b27dcd230b46c; valaddr_reg:x8;
|
||||
val_offset:30*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 30*8, x9, x5, x6,ld)
|
||||
|
||||
inst_55:// rs1_val == 24358691315317906 and fcsr == 0 and rm_val == 7
|
||||
inst_55:// rs1_val == 24358691315317906 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x568a19c70afc92; valaddr_reg:x8;
|
||||
val_offset:31*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 31*8, x9, x5, x6,ld)
|
||||
|
||||
inst_56:// rs1_val == 59668294213987868 and fcsr == 0 and rm_val == 7
|
||||
inst_56:// rs1_val == 59668294213987868 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xd3fbff58fa6e1c; valaddr_reg:x8;
|
||||
val_offset:32*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 32*8, x9, x5, x6,ld)
|
||||
|
||||
inst_57:// rs1_val == 104291213792325832 and fcsr == 0 and rm_val == 7
|
||||
inst_57:// rs1_val == 104291213792325832 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x172844e6f4930c8; valaddr_reg:x8;
|
||||
val_offset:33*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 33*8, x9, x5, x6,ld)
|
||||
|
||||
inst_58:// rs1_val == 156703057381110404 and fcsr == 0 and rm_val == 7
|
||||
inst_58:// rs1_val == 156703057381110404 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x22cb899b66b3284; valaddr_reg:x8;
|
||||
val_offset:34*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 34*8, x9, x5, x6,ld)
|
||||
|
||||
inst_59:// rs1_val == 428092830716901554 and fcsr == 0 and rm_val == 7
|
||||
inst_59:// rs1_val == 428092830716901554 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x5f0e42951c5b8b2; valaddr_reg:x8;
|
||||
val_offset:35*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 35*8, x9, x5, x6,ld)
|
||||
|
||||
inst_60:// rs1_val == 878257878219487117 and fcsr == 0 and rm_val == 7
|
||||
inst_60:// rs1_val == 878257878219487117 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0xc3032e31475f78d; valaddr_reg:x8;
|
||||
val_offset:36*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 36*8, x9, x5, x6,ld)
|
||||
|
||||
inst_61:// rs1_val == 2086309477244717835 and fcsr == 0 and rm_val == 7
|
||||
inst_61:// rs1_val == 2086309477244717835 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x1cf40f6a72b3cb0b; valaddr_reg:x8;
|
||||
val_offset:37*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 37*8, x9, x5, x6,ld)
|
||||
|
||||
inst_62:// rs1_val == 3035559518675506972 and fcsr == 0 and rm_val == 7
|
||||
inst_62:// rs1_val == 3035559518675506972 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x2a20794c9535971c; valaddr_reg:x8;
|
||||
val_offset:38*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 38*8, x9, x5, x6,ld)
|
||||
|
||||
inst_63:// rs1_val == 9184267462870993263 and fcsr == 0 and rm_val == 7
|
||||
inst_63:// rs1_val == 9184267462870993263 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x7f751298de9a896f; valaddr_reg:x8;
|
||||
val_offset:39*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.l, f31, x31, dyn, 0, 0, x8, 39*8, x9, x5, x6,ld)
|
||||
|
||||
inst_64:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
inst_64:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.l ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:40*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 05:17:20 2023 GMT
|
||||
// timestamp : Mon Mar 25 04:46:01 2024 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
|
||||
@ -15,11 +15,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup.
|
||||
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64IFD_Zicsr_Zfh")
|
||||
RVTEST_ISA("RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
@ -29,31 +29,31 @@ RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x3, 0*8, x4, x1, x2,ld)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f30, x30, dyn, 0, 0, x3, 1*8, x4, x1, x2,ld)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 18446744073709551615 and fcsr == 0 and rm_val == 7
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 18446744073709551615 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x29; dest:f29; op1val:0xffffffffffffffff; valaddr_reg:x3;
|
||||
val_offset:2*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f29, x29, dyn, 0, 0, x3, 2*8, x4, x1, x2,ld)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 10540517427298422784 and fcsr == 0 and rm_val == 7
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 10540517427298422784 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x28; dest:f28; op1val:0x924770c10aefd000; valaddr_reg:x3;
|
||||
val_offset:3*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 05:17:20 2023 GMT
|
||||
// timestamp : Mon Mar 25 04:46:01 2024 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
|
||||
@ -15,11 +15,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup.
|
||||
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64IFD_Zicsr_Zfh")
|
||||
RVTEST_ISA("RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
@ -29,399 +29,399 @@ RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x3, 0*8, x4, x1, x2,ld)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f30, x30, dyn, 0, 0, x3, 1*8, x4, x1, x2,ld)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:2*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f29, x29, dyn, 0, 0, x3, 2*8, x4, x1, x2,ld)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
|
||||
val_offset:3*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f28, x28, dyn, 0, 0, x3, 3*8, x4, x1, x2,ld)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
|
||||
val_offset:4*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f27, x27, dyn, 0, 0, x3, 4*8, x4, x1, x2,ld)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
|
||||
val_offset:5*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f26, x26, dyn, 0, 0, x3, 5*8, x4, x1, x2,ld)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
|
||||
val_offset:6*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f25, x25, dyn, 0, 0, x3, 6*8, x4, x1, x2,ld)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
|
||||
val_offset:7*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f24, x24, dyn, 0, 0, x3, 7*8, x4, x1, x2,ld)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
|
||||
val_offset:8*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f23, x23, dyn, 0, 0, x3, 8*8, x4, x1, x2,ld)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
|
||||
val_offset:9*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f22, x22, dyn, 0, 0, x3, 9*8, x4, x1, x2,ld)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
|
||||
val_offset:10*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f21, x21, dyn, 0, 0, x3, 10*8, x4, x1, x2,ld)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
|
||||
val_offset:11*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f20, x20, dyn, 0, 0, x3, 11*8, x4, x1, x2,ld)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
|
||||
val_offset:12*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f19, x19, dyn, 0, 0, x3, 12*8, x4, x1, x2,ld)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
|
||||
val_offset:13*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f18, x18, dyn, 0, 0, x3, 13*8, x4, x1, x2,ld)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
|
||||
val_offset:14*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f17, x17, dyn, 0, 0, x3, 14*8, x4, x1, x2,ld)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
|
||||
val_offset:15*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f16, x16, dyn, 0, 0, x3, 15*8, x4, x1, x2,ld)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
|
||||
val_offset:16*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f15, x15, dyn, 0, 0, x3, 16*8, x4, x1, x2,ld)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f14, x14, dyn, 0, 0, x3, 17*8, x4, x1, x2,ld)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f13, x13, dyn, 0, 0, x3, 18*8, x4, x1, x2,ld)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f12, x12, dyn, 0, 0, x3, 19*8, x4, x1, x2,ld)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f11, x11, dyn, 0, 0, x3, 20*8, x4, x1, x2,ld)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f10, x10, dyn, 0, 0, x3, 21*8, x4, x1, x2,ld)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f9, x9, dyn, 0, 0, x3, 22*8, x4, x1, x2,ld)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f8, x8, dyn, 0, 0, x3, 23*8, x4, x1, x2,ld)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f7, x7, dyn, 0, 0, x8, 0*8, x9, x1, x2,ld)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f6, x6, dyn, 0, 0, x8, 1*8, x9, x1, x2,ld)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f5, x5, dyn, 0, 0, x8, 2*8, x9, x1, x6,ld)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f4, x4, dyn, 0, 0, x8, 3*8, x9, x5, x6,ld)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f3, x3, dyn, 0, 0, x8, 4*8, x9, x5, x6,ld)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f2, x2, dyn, 0, 0, x8, 5*8, x9, x5, x6,ld)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f1, x1, dyn, 0, 0, x8, 6*8, x9, x5, x6,ld)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f0, x0, dyn, 0, 0, x8, 7*8, x9, x5, x6,ld)
|
||||
|
||||
inst_32:// rs1_val == 4035756470 and fcsr == 0 and rm_val == 7
|
||||
inst_32:// rs1_val == 4035756470 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xf08cc1b6; valaddr_reg:x8;
|
||||
val_offset:8*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 8*8, x9, x5, x6,ld)
|
||||
|
||||
inst_33:// rs1_val == 6929185936 and fcsr == 0 and rm_val == 7
|
||||
inst_33:// rs1_val == 6929185936 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x19d02fc90; valaddr_reg:x8;
|
||||
val_offset:9*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 9*8, x9, x5, x6,ld)
|
||||
|
||||
inst_34:// rs1_val == 8607351303 and fcsr == 0 and rm_val == 7
|
||||
inst_34:// rs1_val == 8607351303 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x20109c207; valaddr_reg:x8;
|
||||
val_offset:10*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 10*8, x9, x5, x6,ld)
|
||||
|
||||
inst_35:// rs1_val == 22050244097 and fcsr == 0 and rm_val == 7
|
||||
inst_35:// rs1_val == 22050244097 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x5224c0601; valaddr_reg:x8;
|
||||
val_offset:11*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 11*8, x9, x5, x6,ld)
|
||||
|
||||
inst_36:// rs1_val == 51102363774 and fcsr == 0 and rm_val == 7
|
||||
inst_36:// rs1_val == 51102363774 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xbe5f0307e; valaddr_reg:x8;
|
||||
val_offset:12*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 12*8, x9, x5, x6,ld)
|
||||
|
||||
inst_37:// rs1_val == 131206879410 and fcsr == 0 and rm_val == 7
|
||||
inst_37:// rs1_val == 131206879410 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x1e8c8a18b2; valaddr_reg:x8;
|
||||
val_offset:13*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 13*8, x9, x5, x6,ld)
|
||||
|
||||
inst_38:// rs1_val == 268160711063 and fcsr == 0 and rm_val == 7
|
||||
inst_38:// rs1_val == 268160711063 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x3e6f9fb997; valaddr_reg:x8;
|
||||
val_offset:14*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 14*8, x9, x5, x6,ld)
|
||||
|
||||
inst_39:// rs1_val == 453482173015 and fcsr == 0 and rm_val == 7
|
||||
inst_39:// rs1_val == 453482173015 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x6995a4d257; valaddr_reg:x8;
|
||||
val_offset:15*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 15*8, x9, x5, x6,ld)
|
||||
|
||||
inst_40:// rs1_val == 813522083007 and fcsr == 0 and rm_val == 7
|
||||
inst_40:// rs1_val == 813522083007 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xbd69b1dcbf; valaddr_reg:x8;
|
||||
val_offset:16*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 16*8, x9, x5, x6,ld)
|
||||
|
||||
inst_41:// rs1_val == 1168389695644 and fcsr == 0 and rm_val == 7
|
||||
inst_41:// rs1_val == 1168389695644 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x1100973e89c; valaddr_reg:x8;
|
||||
val_offset:17*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 17*8, x9, x5, x6,ld)
|
||||
|
||||
inst_42:// rs1_val == 3524006078498 and fcsr == 0 and rm_val == 7
|
||||
inst_42:// rs1_val == 3524006078498 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x3347f216822; valaddr_reg:x8;
|
||||
val_offset:18*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 18*8, x9, x5, x6,ld)
|
||||
|
||||
inst_43:// rs1_val == 5032232323694 and fcsr == 0 and rm_val == 7
|
||||
inst_43:// rs1_val == 5032232323694 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x493a86b8a6e; valaddr_reg:x8;
|
||||
val_offset:19*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 19*8, x9, x5, x6,ld)
|
||||
|
||||
inst_44:// rs1_val == 10221399934292 and fcsr == 0 and rm_val == 7
|
||||
inst_44:// rs1_val == 10221399934292 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x94bdae98554; valaddr_reg:x8;
|
||||
val_offset:20*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 20*8, x9, x5, x6,ld)
|
||||
|
||||
inst_45:// rs1_val == 31117680965175 and fcsr == 0 and rm_val == 7
|
||||
inst_45:// rs1_val == 31117680965175 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x1c4d2651f637; valaddr_reg:x8;
|
||||
val_offset:21*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 21*8, x9, x5, x6,ld)
|
||||
|
||||
inst_46:// rs1_val == 45718214482007 and fcsr == 0 and rm_val == 7
|
||||
inst_46:// rs1_val == 45718214482007 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x299499ef1857; valaddr_reg:x8;
|
||||
val_offset:22*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 22*8, x9, x5, x6,ld)
|
||||
|
||||
inst_47:// rs1_val == 132508745935081 and fcsr == 0 and rm_val == 7
|
||||
inst_47:// rs1_val == 132508745935081 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x788418bb28e9; valaddr_reg:x8;
|
||||
val_offset:23*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 23*8, x9, x5, x6,ld)
|
||||
|
||||
inst_48:// rs1_val == 194479587133174 and fcsr == 0 and rm_val == 7
|
||||
inst_48:// rs1_val == 194479587133174 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xb0e0ceb506f6; valaddr_reg:x8;
|
||||
val_offset:24*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 24*8, x9, x5, x6,ld)
|
||||
|
||||
inst_49:// rs1_val == 477767642386861 and fcsr == 0 and rm_val == 7
|
||||
inst_49:// rs1_val == 477767642386861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x1b286f29c11ad; valaddr_reg:x8;
|
||||
val_offset:25*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 25*8, x9, x5, x6,ld)
|
||||
|
||||
inst_50:// rs1_val == 1064659746632576 and fcsr == 0 and rm_val == 7
|
||||
inst_50:// rs1_val == 1064659746632576 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x3c84d6a013380; valaddr_reg:x8;
|
||||
val_offset:26*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 26*8, x9, x5, x6,ld)
|
||||
|
||||
inst_51:// rs1_val == 1449063015970349 and fcsr == 0 and rm_val == 7
|
||||
inst_51:// rs1_val == 1449063015970349 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x525ea4652f62d; valaddr_reg:x8;
|
||||
val_offset:27*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 27*8, x9, x5, x6,ld)
|
||||
|
||||
inst_52:// rs1_val == 3454382579804098 and fcsr == 0 and rm_val == 7
|
||||
inst_52:// rs1_val == 3454382579804098 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xc45be1e9667c2; valaddr_reg:x8;
|
||||
val_offset:28*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 28*8, x9, x5, x6,ld)
|
||||
|
||||
inst_53:// rs1_val == 7228908657904184 and fcsr == 0 and rm_val == 7
|
||||
inst_53:// rs1_val == 7228908657904184 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x19aea774ab0a38; valaddr_reg:x8;
|
||||
val_offset:29*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 29*8, x9, x5, x6,ld)
|
||||
|
||||
inst_54:// rs1_val == 12147253371253868 and fcsr == 0 and rm_val == 7
|
||||
inst_54:// rs1_val == 12147253371253868 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x2b27dcd230b46c; valaddr_reg:x8;
|
||||
val_offset:30*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 30*8, x9, x5, x6,ld)
|
||||
|
||||
inst_55:// rs1_val == 24358691315317906 and fcsr == 0 and rm_val == 7
|
||||
inst_55:// rs1_val == 24358691315317906 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x568a19c70afc92; valaddr_reg:x8;
|
||||
val_offset:31*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 31*8, x9, x5, x6,ld)
|
||||
|
||||
inst_56:// rs1_val == 59668294213987868 and fcsr == 0 and rm_val == 7
|
||||
inst_56:// rs1_val == 59668294213987868 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xd3fbff58fa6e1c; valaddr_reg:x8;
|
||||
val_offset:32*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 32*8, x9, x5, x6,ld)
|
||||
|
||||
inst_57:// rs1_val == 104291213792325832 and fcsr == 0 and rm_val == 7
|
||||
inst_57:// rs1_val == 104291213792325832 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x172844e6f4930c8; valaddr_reg:x8;
|
||||
val_offset:33*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 33*8, x9, x5, x6,ld)
|
||||
|
||||
inst_58:// rs1_val == 156703057381110404 and fcsr == 0 and rm_val == 7
|
||||
inst_58:// rs1_val == 156703057381110404 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x22cb899b66b3284; valaddr_reg:x8;
|
||||
val_offset:34*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 34*8, x9, x5, x6,ld)
|
||||
|
||||
inst_59:// rs1_val == 428092830716901554 and fcsr == 0 and rm_val == 7
|
||||
inst_59:// rs1_val == 428092830716901554 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x5f0e42951c5b8b2; valaddr_reg:x8;
|
||||
val_offset:35*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 35*8, x9, x5, x6,ld)
|
||||
|
||||
inst_60:// rs1_val == 878257878219487117 and fcsr == 0 and rm_val == 7
|
||||
inst_60:// rs1_val == 878257878219487117 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0xc3032e31475f78d; valaddr_reg:x8;
|
||||
val_offset:36*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 36*8, x9, x5, x6,ld)
|
||||
|
||||
inst_61:// rs1_val == 2086309477244717835 and fcsr == 0 and rm_val == 7
|
||||
inst_61:// rs1_val == 2086309477244717835 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x1cf40f6a72b3cb0b; valaddr_reg:x8;
|
||||
val_offset:37*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 37*8, x9, x5, x6,ld)
|
||||
|
||||
inst_62:// rs1_val == 3035559518675506972 and fcsr == 0 and rm_val == 7
|
||||
inst_62:// rs1_val == 3035559518675506972 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x2a20794c9535971c; valaddr_reg:x8;
|
||||
val_offset:38*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 38*8, x9, x5, x6,ld)
|
||||
|
||||
inst_63:// rs1_val == 9184267462870993263 and fcsr == 0 and rm_val == 7
|
||||
inst_63:// rs1_val == 9184267462870993263 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x7f751298de9a896f; valaddr_reg:x8;
|
||||
val_offset:39*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.lu, f31, x31, dyn, 0, 0, x8, 39*8, x9, x5, x6,ld)
|
||||
|
||||
inst_64:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
inst_64:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.lu ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:40*8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user