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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed unnecessary display from testbench.
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8885c32f7c
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@ -1 +1 @@
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../wsim rv64gc arch64i
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wsim rv64gc arch64i
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@ -108,8 +108,6 @@ module testbench;
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TEST = "none";
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if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
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INSTR_LIMIT = 0;
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$display("INSTR_LIMIT = ", INSTR_LIMIT);
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// pick tests based on modes supported
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//tests = '{};
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@ -246,7 +244,7 @@ module testbench;
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logic ResetCntRst;
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logic CopyRAM;
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string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
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string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
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integer begin_signature_addr, end_signature_addr, signature_size;
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assign ResetThreshold = 3'd5;
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@ -338,8 +336,9 @@ module testbench;
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else if(TEST == "buildroot") begin
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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uartoutfilename = {"logs/",TEST,"_uart.out"};
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$system("rm ",uartoutfilename); // Delete existing UARToutfile
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uartoutfilename = {"logs/", TEST, "_uart.out"};
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rmCmd = {"rm ", uartoutfilename};
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$system(rmCmd); // Delete existing UARToutfile
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end
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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@ -582,7 +581,7 @@ module testbench;
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// Append UART output to file for tests
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always @(posedge clk) begin
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if (TEST == "buildroot") begin
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if (P.UART_SUPPORTED & TEST == "buildroot") begin
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if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
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memFile = $fopen(uartoutfilename, "ab");
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$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
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