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https://github.com/openhwgroup/cvw
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Flushing uart.out file to observe progress
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parent
45196a9959
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@ -350,8 +350,7 @@ module testbench;
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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uartoutfilename = {"logs/", TEST, "_uart.out"};
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uartoutfile = $fopen(uartoutfilename, "wb"); // delete UART output file
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$fclose(uartoutfilename);
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uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
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end
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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@ -599,9 +598,8 @@ module testbench;
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always @(posedge clk) begin
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if (TEST == "buildroot") begin
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if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
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uartoutfile = $fopen(uartoutfilename, "a"); // append characters one at a time so we see a consistent log appearing during the run
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$fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
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$fclose(uartoutfilename);
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$fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); // append characters one at a time so we see a consistent log appearing during the run
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$fflush(uartoutfile);
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end
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end
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end
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