Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Changed testbench to use fopen instead of opening and closing uartfile whenever writing

Browse Source
This commit is contained in:
slmnemo 2024-04-20 16:56:54 -07:00
parent 770d918268
commit 354d447269
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
testbench/testbench.sv
View File

@ -256,6 +256,7 @@ module testbench;
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
integer begin_signature_addr, end_signature_addr, signature_size;
integer uartoutfile;
assign ResetThreshold = 3'd5;
@ -355,8 +356,7 @@ module testbench;
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
uartoutfilename = {"logs/", TEST, "_uart.out"};
rmCmd = {"rm -f ", uartoutfilename};
unused_int = system(rmCmd); // Delete existing UARToutfile
uartoutfile = $fopen(uartoutfilename, "wb");
end
else memfilename = {pathname, tests[test], ".elf.memfile"};
if (riscofTest) begin
@ -383,6 +383,8 @@ module testbench;
always @(posedge Validate) // added
`endif
if(Validate) begin
if (TEST == "buildroot")
$fclose(uartoutfile);
if (TEST == "embench") begin
// Writes contents of begin_signature to .sim.output file
// this contains instret and cycles for start and end of test run, used by embench
@ -602,9 +604,7 @@ module testbench;
always @(posedge clk) begin
if (TEST == "buildroot") begin
if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
$fclose(memFile);
$fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
end
end
end