Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

script cleanup

Browse Source
This commit is contained in:
David Harris 2024-04-20 17:22:31 -07:00
parent 338f37b570
commit a1876b1e7c
4 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bin/wsim
View File

@ -82,6 +82,6 @@ elif (args.sim == "vcs"):
if (args.gui):
print("GUI option not available for VCS")
exit(1)
cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite
cmd = cd + "; ./run_vcs " + args.config + " " + "\""+args.testsuite+"\""
print(cmd)
os.system(cmd)

3
sim/vcs/run_vcs
View File

@ -27,6 +27,7 @@ clean() {
# Clean and run simulation with VCS
clean
#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS]
vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
./$OUTPUT | tee program.out

1
testbench/common/DCacheFlushFSM.sv
View File

@ -29,7 +29,6 @@
module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
(input logic clk,
input logic reset,
input logic start,
output logic done);

16
testbench/testbench.sv
View File

@ -508,17 +508,17 @@ module testbench;
////////////////////////////////////////////////////////////////////////////////
// instantiate device to be tested
assign GPIOIN = 0;
assign UARTSin = 1;
assign SPIIn = 0;
assign GPIOIN = '0;
assign UARTSin = 1'b1;
assign SPIIn = 1'b0;
if(P.EXT_MEM_SUPPORTED) begin
ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
end else begin
assign HREADYEXT = 1;
assign {HRESPEXT, HRDATAEXT} = 0;
assign HREADYEXT = 1'b1;
assign {HRESPEXT, HRDATAEXT} = '0;
end
if(P.SDC_SUPPORTED) begin : sdcard
@ -534,9 +534,9 @@ module testbench;
assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
assign SDCDatIn = SDCDat;
-----/\----- EXCLUDED -----/\----- */
assign SDCIntr = 0;
assign SDCIntr = 1'b0;
end else begin
assign SDCIntr = 0;
assign SDCIntr = 1'b0;
end
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
@ -621,7 +621,7 @@ module testbench;
//assign DCacheFlushStart = TestComplete;
end
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
if(P.ZICSR_SUPPORTED) begin
logic [P.XLEN-1:0] Minstret;