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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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David Harris 2024-04-03 06:51:24 -07:00
commit 8741b01818
2 changed files with 2 additions and 2 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b

2
testbench/testbench.sv
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@ -479,7 +479,7 @@ module testbench;
assign SPIIn = 0;
if(P.EXT_MEM_SUPPORTED) begin
ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
end else begin