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Removed delays from cacheLRU and testbench

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This commit is contained in:
David Harris 2024-03-25 12:20:25 -07:00
parent 690338b758
commit 0caab3c0c9
3 changed files with 6 additions and 6 deletions
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4
src/cache/cacheLRU.sv vendored
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@ -149,8 +149,8 @@ module cacheLRU
for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
else if(CacheEn) begin
// Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU;
else CurrLRU = #1 LRUMemory[CacheSetTag];
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;
else CurrLRU = LRUMemory[CacheSetTag];
if(LRUWriteEn) LRUMemory[PAdr] = NextLRU;
end
end

4
testbench/testbench-xcelium.sv
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@ -216,8 +216,8 @@ module testbench;
end
always_ff @(posedge clk)
if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
else CurrState <= #1 NextState;
if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
else CurrState <= NextState;
// fsm next state logic
always_comb begin

4
testbench/testbench.sv
View File

@ -248,8 +248,8 @@ module testbench;
end
always_ff @(posedge clk)
if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
else CurrState <= #1 NextState;
if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
else CurrState <= NextState;
// fsm next state logic
always_comb begin