Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.

Browse Source
This commit is contained in:
David Harris 2024-03-14 19:03:57 -07:00
parent cb610e10da
commit 9ff9f9e0ae
8 changed files with 3172 additions and 1201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
testbench/tests.vh
View File

@ -1209,7 +1209,8 @@ string imperas32f[] = '{
};
string arch64zfh_fma[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/Zfh/src/fmadd_b15-01.S",
"rv64i_m/Zfh/src/fmsub_b15-01.S",
"rv64i_m/Zfh/src/fnmadd_b15-01.S",
@ -1367,7 +1368,8 @@ string imperas32f[] = '{
};
string arch64zfh_divsqrt[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/Zfh/src/fdiv_b20-01.S",
"rv64i_m/Zfh/src/fdiv_b1-01.S",
"rv64i_m/Zfh/src/fdiv_b2-01.S",
@ -1391,7 +1393,8 @@ string imperas32f[] = '{
};
string arch64zfh[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/Zfh/src/fadd_b10-01.S",
"rv64i_m/Zfh/src/fadd_b1-01.S",
"rv64i_m/Zfh/src/fadd_b11-01.S",
@ -2056,7 +2059,8 @@ string arch64zknh[] = '{
};
string arch32zfh_divsqrt[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/Zfh/src/fdiv_b20-01.S",
"rv32i_m/Zfh/src/fdiv_b1-01.S",
"rv32i_m/Zfh/src/fdiv_b2-01.S",
@ -2080,7 +2084,8 @@ string arch64zknh[] = '{
};
string arch32zfh[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/Zfh/src/fadd_b10-01.S",
"rv32i_m/Zfh/src/fadd_b1-01.S",
"rv32i_m/Zfh/src/fadd_b11-01.S",
@ -2206,7 +2211,8 @@ string arch64zknh[] = '{
};
string arch32zfaf[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/F_Zfa/src/fleq_b1-01.S",
"rv32i_m/F_Zfa/src/fleq_b19-01.S",
"rv32i_m/F_Zfa/src/fli.s-01.S",
@ -2222,7 +2228,8 @@ string arch64zknh[] = '{
};
string arch32zfad[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
@ -2258,7 +2265,8 @@ string arch64zknh[] = '{
};
string arch64zfaf[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/F_Zfa/src/fleq_b1-01.S",
"rv64i_m/F_Zfa/src/fleq_b19-01.S",
"rv64i_m/F_Zfa/src/fli.s-01.S",
@ -2272,9 +2280,10 @@ string arch64zknh[] = '{
};
string arch64zfad[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
// "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S", // temporarily excluded because Sail produces wrong signature https://github.com/riscv/sail-riscv/issues/388
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S",
@ -2301,7 +2310,8 @@ string arch64zknh[] = '{
};
string arch32zfh_fma[] = '{
`RISCVARCHTEST,
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/Zfh/src/fmadd_b15-01.S",
"rv32i_m/Zfh/src/fmsub_b15-01.S",
"rv32i_m/Zfh/src/fnmadd_b15-01.S",

2
tests/riscof/Makefile
View File

@ -42,6 +42,8 @@ wally32:
wally64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
# Also copy F and D tests to RV64
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
#wally32e:
# riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run

3180
tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h vendored
View File

File diff suppressed because it is too large Load Diff

8
tests/wally-riscv-arch-test/riscv-test-suite/env/encoding.h vendored
View File

@ -37,6 +37,7 @@
#define MSTATUS_HPP 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_VS 0x00000600
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_SUM 0x00040000
@ -776,6 +777,7 @@
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_HEDELEG 0x602
#define CSR_HPMCOUNTER3 0xc03
#define CSR_HPMCOUNTER4 0xc04
#define CSR_HPMCOUNTER5 0xc05
@ -805,6 +807,8 @@
#define CSR_HPMCOUNTER29 0xc1d
#define CSR_HPMCOUNTER30 0xc1e
#define CSR_HPMCOUNTER31 0xc1f
#define CSR_VSATP 0x280
#define CSR_HSTATUS 0x600
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
@ -815,7 +819,9 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
#define CSR_SEDELEG 0x102
#define CSR_MSTATUS 0x300
#define CSR_MSTATUSH 0x310
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
@ -1310,6 +1316,8 @@ DECLARE_CSR(stval, CSR_STVAL)
DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(satp, CSR_SATP)
DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(mstatush, CSR_MSTATUSH)
DECLARE_CSR(hstatus, CSR_HSTATUS)
DECLARE_CSR(misa, CSR_MISA)
DECLARE_CSR(medeleg, CSR_MEDELEG)
DECLARE_CSR(mideleg, CSR_MIDELEG)

1139
tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h vendored Normal file
View File

File diff suppressed because it is too large Load Diff

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -19,7 +19,7 @@ FFFFFFFF # stimecmp low bits
00000000
00000003 # mcause from Breakpoint
00000000
80000408 # mtval of breakpoint instruction adress (0x80000400)
80000458 # mtval of breakpoint instruction adress (0x80000458)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -131,7 +131,7 @@ FFFFFFFF # stimecmp low bits
00000000
00000003 # mcause from Breakpoint
00000000
80000408 # mtval of breakpoint instruction adress (0x80000400)
80000458 # mtval of breakpoint instruction adress (0x80000458)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -20,7 +20,7 @@
00000000
00000003 # scause from Breakpoint
00000000
80000408 # stval of breakpoint instruction adress (0x80000400)
80000458 # stval of breakpoint instruction adress (0x80000400)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -122,7 +122,7 @@
00000000
00000003 # scause from Breakpoint
00000000
80000408 # stval of breakpoint instruction adress (0x80000400)
80000458 # stval of breakpoint instruction adress (0x80000400)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -20,7 +20,7 @@
00000000
00000003 # scause from Breakpoint
00000000
80000408 # stval of breakpoint instruction adress (0x80000400)
80000458 # stval of breakpoint instruction adress (0x80000400)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
@ -116,7 +116,7 @@
00000000
00000003 # scause from Breakpoint
00000000
80000408 # stval of breakpoint instruction adress (0x80000400)
80000458 # stval of breakpoint instruction adress (0x80000400)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000