cvw/testbench
Rose Thompson 038aae388b Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name.  Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf.  Waiting several
cycles does not work.  rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
..
common Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide 2024-05-15 09:23:24 -07:00
coverage pmp coverage 2024-05-02 11:53:32 -07:00
sdc Remove all #delay from non-testbench. 2024-03-16 11:20:32 -07:00
testbench_fp.sv Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes 2024-05-13 15:16:00 -07:00
testbench-imperas.sv Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now. 2024-05-17 16:08:14 -05:00
testbench.sv Yay. Finally found the issue with the integrated testbench.sv and imperasDV. 2024-05-17 16:45:01 -05:00
tests_fp.vh testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./ 2024-04-06 08:22:39 -07:00
tests.vh Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases 2024-05-11 22:32:51 -07:00
wallywrapper.sv Verilator improvements 2023-11-04 03:21:07 -07:00