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1011 Commits

Author SHA1 Message Date
Rose Thompson
36ca64c567 At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
657409aec5 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
6041bf20b3 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
834c0df697 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
449abef823 Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
Rose Thompson
06b5a92eff Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
4cd0584a11 Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00
Rose Thompson
12763b7297 begin implemenation of Zicclsm. 2023-10-26 11:51:20 -05:00
Rose Thompson
3322ff915e Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
Rose Thompson
694ec18934 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
David Harris
6e7c0547a1 Modified log2 coding to avoid synthesis warning 2023-10-19 11:16:02 -07:00
David Harris
48d42c1e7c Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8 always working after reg bit swizzle changes 2023-10-13 14:22:32 -07:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
e02d3577ec Fixed issue #412 
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.

The simplest solution is to use CommittedF to delay Exceptions like with Interrupts.  Note this cannot happen with CommittedM.  If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
 2023-10-09 16:03:37 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
aeacb481aa Fixed sutble RAS bug when the stack size was not a power of 2. 2023-09-27 12:00:47 -05:00
Ross Thompson
26e4f6c6ba Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-09-14 10:16:54 -05:00
Ross Thompson
11a3fd9314 Slight modification to cachefsm. 2023-09-05 14:07:58 -05:00
Ross Thompson
22c519f2df Merge pull request #407 from davidharrishmc/dev 
initial spill logic improvement
 2023-09-05 13:29:37 -05:00
Ross Thompson
85ba53eeaf Merge pull request #406 from magpyed/cachesim_fix 
Properly gate LRUWriteEn with ~FlushStage
 2023-09-05 11:10:58 -05:00
David Harris
8f12c6f9a1 initial spill logic improvement 2023-09-03 04:21:13 -07:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
Limnanthes Serafini
6c78942685 Properly gate LRUWriteEn with ~FlushStage 2023-09-01 23:31:02 -07:00
David Harris
e75ceb044f Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
Kevin Kim
e4b0ab1472 Merge branch 'openhwgroup:main' into synth_wrapper_gen 2023-08-28 09:03:10 -07:00
Kevin Kim
ea46280146 make synth integerates wrapper generation and runs synth on wrapper 2023-08-28 09:02:56 -07:00
Ross Thompson
d892afc574 Merge pull request #398 from davidharrishmc/dev 
Completed basic tests of svnapot and svpbmt
 2023-08-28 09:10:20 -05:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
Kevin Kim
dabd15e029 synth works 2023-08-26 21:11:21 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
f7b50f4721 Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
David Harris
0e16203cd8 Merge pull request #393 from ross144/main 
Implemented and tested CBOZ instruction
 2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
Ross Thompson
99455ad851 Fixed minor performance bug with CBOZ. 2023-08-24 17:08:20 -05:00
Ross Thompson
914b6f9734 Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
David Harris
f5dab9f2fe Check for legal SATP mode values 2023-08-24 05:18:04 -07:00
Ross Thompson
00e65c4ae7 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
Ross Thompson
45a7dfba28 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-08-23 09:15:13 -05:00
Jacob Pease
140d246fb5 Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP. 2023-08-22 16:25:56 -05:00
Ross Thompson
c2a9fbb1fc Fixed bug with the cbo.inval clearing already cleared lines. 2023-08-21 17:51:51 -05:00
Ross Thompson
05d590b0b9 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
4eeba9bed9 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
Ross Thompson
5c408454b8 Might have working cbo clean and flush instructions. 2023-08-18 14:48:21 -05:00
Ross Thompson
21129dde71 Fixed cbo instruction decode. 2023-08-18 11:32:30 -05:00
Ross Thompson
9dcc70d6c1 Updated the hazard logic for CMO operations. 2023-08-17 17:58:49 -05:00
Ross Thompson
072126b967 Found first bug in CMO implementation. 2023-08-17 16:57:54 -05:00
Ross Thompson
f9df1fda23 CMOZ now implemented in the D cache. 2023-08-17 12:46:40 -05:00
Ross Thompson
624b3e3ab2 Added clean and flush to cache fsm. 2023-08-16 14:23:56 -05:00
Ross Thompson
5281077531 More progress towards cmo. 2023-08-15 18:17:15 -05:00
Ross Thompson
9f37fef145 The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. 2023-08-14 16:39:18 -05:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
faaf43fa10 Merge pull request #372 from davidharrishmc/dev 
PLIC part select warnings fixed
 2023-07-31 11:28:28 -04:00
David Harris
6ff2b0cc2c Merge pull request #373 from harshinisrinath1001/main 
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
 2023-07-30 22:46:44 -07:00
Harshini Srinath
7ed4cf97ed Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
603ed2160e Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
acbbe7941a Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
e4de9ae87c Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
4c1a07eb9c Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
1badc8a8c5 Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
41555b149e Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8e97224cd7 Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
469b03577d Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
141384f60f Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
bbbd5f6b2d Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
d7b2d84124 Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
b129068a92 Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
49823ccd45 Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
36108e4b52 Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
d88b2fd9c1 Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
d69d0ececc Fixed spacing 2023-07-30 16:57:57 -07:00
David Harris
d58ece3d44 renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
28823aca6e Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
7e06775135 Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
15dc76310e Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
2dac02c14c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
David Harris
ca62487e4c Formatting cleanup 2023-07-25 05:11:38 -07:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
f895898d22 Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
c0966c32e5 Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
538efaf771 Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
af0e33209f Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
42e6364b3d Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
c82638774f Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
Ross Thompson
50bc679fef Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Jacob Pease
b3aaa87cba Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
David Harris
644afa16cd Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
4c4eb080ee RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
12beada55b Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
beaec570c7 Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
e713ba8d3e MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
cdf73d3b51 Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
e4555dc4af Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
369e8fb5ec Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
869a7cb827 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
a963e50e88 It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
df56ff73c0 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
c000366d3e closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
David Harris
269bb688ea Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
410ef01627 fixed spacing in fdivsqrt 2023-07-04 11:27:36 -07:00
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
723b8266cb Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
c48283801a Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
61208e486c Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
41e9f20943 improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
e34ef4d636 improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
d930be332e Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
c383407d5c Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
c44d4321fb FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
bdc5656ef3 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
3ca271b6a7 Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
9e839988dc Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
9f88848832 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
a62211bad1 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
d3aebc00d4 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
dd7c13cc2d Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
b4469fd3bf Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
85a513e542 Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
b5354a811e Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
85b982f569 Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
59178a2e56 Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00
Harshini Srinath
d02891d244 Update rom_ahb.sv 
Program clean up
 2023-06-15 10:13:15 -07:00
Harshini Srinath
e227f71d46 Update ram_ahb.sv 
Program clean up
 2023-06-15 10:10:38 -07:00
Harshini Srinath
57f4c8a3e4 Update plic_apb.sv 
Program clean up
 2023-06-15 10:08:16 -07:00
Harshini Srinath
cf25e9ce49 Update gpio_apb.sv 
Program clean up
 2023-06-15 10:04:28 -07:00
Harshini Srinath
a8fa38ff14 Update clint_apb.sv 
Program clean up
 2023-06-15 09:59:11 -07:00
David Harris
325a670435 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-15 07:01:44 -07:00
Ross Thompson
60e87b08c4 Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. 2023-06-14 15:28:58 -05:00
Harshini Srinath
3593762cfa Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
David Harris
430537a052 Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
David Harris
9da4005a1e Removed *** from UART code 2023-06-14 08:47:01 -07:00
David Harris
5a2bcb917f Removed QEMU from UART 2023-06-14 08:39:01 -07:00
Harshini Srinath
3f8cd8932c Update csrs.sv 
Program clean up
 2023-06-13 22:16:43 -07:00
Harshini Srinath
12af05da02 Update csrm.sv 
Program clean up
 2023-06-13 22:08:06 -07:00
Harshini Srinath
a213f7d5a4 Update csrc.sv 
Program clean up
 2023-06-13 21:54:47 -07:00
Harshini Srinath
6aba0187d7 Update csr.sv 
Program clean up
 2023-06-13 21:12:49 -07:00
harshini
8570b2f332 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
9e1f03f93b Update ahbapbbridge.sv 
Program clean up
 2023-06-12 20:49:46 -07:00
Harshini Srinath
2c6322647f Update trap.sv 
Program clean up
 2023-06-12 20:31:44 -07:00
Harshini Srinath
dba1a77e5f Update privmode.sv 
Program clean up
 2023-06-12 20:27:48 -07:00
Harshini Srinath
63a7649179 Update privileged.sv 
Program clean up
 2023-06-12 20:26:07 -07:00
Harshini Srinath
d2a41a6422 Update csru.sv 
Program clean up
 2023-06-12 20:21:55 -07:00
Harshini Srinath
6866a9c541 Update csrsr.sv 
Program clean up
 2023-06-12 20:19:47 -07:00
Harshini Srinath
fbdf76629f Update csrsr.sv 
Program clean up
 2023-06-12 20:15:29 -07:00
Harshini Srinath
120cde2aea Update csrs.sv 
Program clean up
 2023-06-12 19:53:41 -07:00
Harshini Srinath
6305412d57 Update csrm.sv 
Program clean up
 2023-06-12 19:42:45 -07:00
Harshini Srinath
61d50a18da Update csri.sv 
Program clean up
 2023-06-12 19:32:04 -07:00
Harshini Srinath
02a11278fc Update csrc.sv 
Program clean up
 2023-06-12 19:03:34 -07:00
Harshini Srinath
a2645dd576 Update csr.sv 
Program clean up
 2023-06-12 18:51:37 -07:00
Harshini Srinath
a1a9d668c5 Update pmpchecker.sv 
Program clean up
 2023-06-12 18:44:36 -07:00
Harshini Srinath
09ac5b1817 Update pmpadrdec.sv 
Program clean up
 2023-06-12 18:41:47 -07:00
Harshini Srinath
ccb81c84f4 Update pmachecker.sv 
Program clean up
 2023-06-12 18:39:36 -07:00
Harshini Srinath
5a6a932b7e Update mmu.sv 
Program clean up
 2023-06-12 18:36:04 -07:00
Harshini Srinath
a57a619349 Update hptw.sv 
Program clean up
 2023-06-12 18:31:38 -07:00
Harshini Srinath
ec0454111f Update adrdecs.sv 
Program clean up
 2023-06-12 18:22:32 -07:00
Harshini Srinath
b1ee6bfde5 Update adrdec.sv 
Program clean up
 2023-06-12 17:28:21 -07:00
Harshini Srinath
7c51dd18dd Update mul.sv 2023-06-12 14:00:37 -07:00
Harshini Srinath
08459c4cc4 Update mdu.sv 
Program clean up
 2023-06-12 13:54:54 -07:00
Harshini Srinath
bdd2206817 Update div.sv 
Program clean up
 2023-06-12 13:47:09 -07:00
Harshini Srinath
15928c5d7b Update swbytemask.sv 
Program clean up
 2023-06-12 13:37:35 -07:00
Harshini Srinath
f3a7d9030c Update subwordwrite.sv 
Program clean up
 2023-06-12 13:35:27 -07:00
Harshini Srinath
f1f21f0896 Update subwordread.sv 
Program clean up
 2023-06-12 13:31:54 -07:00