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Properly gate LRUWriteEn with ~FlushStage

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Limnanthes Serafini 2023-09-01 23:31:02 -07:00
parent 271c7e43ab
commit 6c78942685
1 changed files with 2 additions and 2 deletions
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4
src/cache/cachefsm.sv vendored
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@ -172,9 +172,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
(CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
// coverage off -item e 1 -fecexprrow 8
assign LRUWriteEn = (CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
assign LRUWriteEn = ((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck) |
(CurrState == STATE_WRITE_LINE) & ~FlushStage;
(CurrState == STATE_WRITE_LINE)) & ~FlushStage;
// exclusion-tag-start: icache flushdirtycontrols
assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty
(CurrState == STATE_WRITE_LINE & (CacheRW[0])) |