Ross Thompson 85ba53eeaf Merge pull request #406 from magpyed/cachesim_fix ... Properly gate LRUWriteEn with ~FlushStage		2023-09-05 11:10:58 -05:00
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cache	Merge pull request #406 from magpyed/cachesim_fix	2023-09-05 11:10:58 -05:00
ebu	Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.	2023-07-21 16:31:26 -05:00
fpu	Merge pull request #372 from davidharrishmc/dev	2023-07-31 11:28:28 -04:00
generic	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00
hazard	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
ieu	Improved tlb and controller coverage; fixed exclusions on broken lines	2023-08-31 00:27:47 -07:00
ifu	Initial implementation of SVNAPOT and SVPBMT does not break regression	2023-08-25 18:33:08 -07:00
lsu	Initial implementation of SVNAPOT and SVPBMT does not break regression	2023-08-25 18:33:08 -07:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker	2023-09-02 12:56:36 -07:00
privileged	Fixed merge conflict for ZICBOP	2023-08-25 18:41:57 -07:00
uncore	Cleaned up lint for plic_apb part select	2023-07-30 02:00:38 -07:00
wally	Initial implementation of SVNAPOT and SVPBMT does not break regression	2023-08-25 18:33:08 -07:00
cvw.sv	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00