minfo test working again with mconfigptr for RV64

sim/Makefile

@@ -49,6 +49,7 @@ clean:
 riscoftests: 
 # 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
 	make -C ../tests/riscof/ 
+	
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
 

sim/imperas.ic

@@ -14,8 +14,14 @@
 --override cpu/add_implicit_Extensions=B 
 --override cpu/bitmanip_version=1.0.0
 
-# ????
+# More extensions
 --override cpu/Zicbom=T
+--override cpu/Zicbop=T
+--override cpu/Zicboz=T
+--override cpu/Svpbmt=T
+# 64 KiB continuous huge pages supported
+--override cpu/Svnapot_page_mask=1<<16
+
 
 #  clarify
 #--override refRoot/cpu/mtvec_sext=F

sim/sim-wally

@@ -1,2 +1,2 @@
-vsim -do "do wally.do rv64gc arch64d"
+vsim -do "do wally.do rv64gc wally64priv"
 

src/ieu/alu.sv

@@ -51,6 +51,8 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
   logic             Asign, Bsign;                                                 // Sign bits of A, B
 
   // Addition
+  // CondMaskB is B for add/sub, or a masked version of B for certain bit manipulation instructions
+  // CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
   assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
   assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
   

src/privileged/csrm.sv

@@ -145,7 +145,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   assign WriteMCOUNTERENM    = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
   assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
 
-  assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
+  assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID | CSRAdrM == MCONFIGPTR);
 
   // CSRs
   flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); 

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -57,6 +57,8 @@ class sail_cSim(pluginTemplate):
             self.isa += 'i'
         if "M" in ispec["ISA"]:
             self.isa += 'm'
+        if "A" in ispec["ISA"]:
+            self.isa += 'a'
         if "C" in ispec["ISA"]:
             self.isa += 'c'
         if "F" in ispec["ISA"]:

tests/riscof/spike/riscof_spike.py

@@ -99,6 +99,8 @@ class spike(pluginTemplate):
           self.isa += 'i'
       if "M" in ispec["ISA"]:
           self.isa += 'm'
+      if "A" in ispec["ISA"]:
+          self.isa += 'a'
       if "F" in ispec["ISA"]:
           self.isa += 'f'
       if "D" in ispec["ISA"]:

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output

@@ -14,5 +14,9 @@
 00000000
 00000011 # confirm read-only permissions of mhartid
 00000000
+00000002 # write to read-only CSR failed with illegal instruction
+00000000
+00000011 # confirm read-only permissions of mconfigptr
+00000000
 0000000b # ecall from terminating tests in M mode
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S

@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h"
 RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo)
 
 INIT_TESTS
 
@@ -34,7 +34,7 @@ CSR_R_ACCESS mvendorid
 CSR_R_ACCESS marchid 
 CSR_R_ACCESS mimpid 
 CSR_R_ACCESS mhartid 
-# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
+CSR_R_ACCESS mconfigptr 
 
 END_TESTS