Rose Thompson
e6902eb4d2
Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
2024-05-17 16:08:14 -05:00
Rose Thompson
d9807bb909
This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
2024-05-17 14:45:37 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
...
Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
...
Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
d4ac53f000
commented legal TEST options
2024-05-13 07:22:30 -07:00
David Harris
75c10bddfa
Moved case.sh to tests/fp
2024-05-13 07:12:16 -07:00
David Harris
d0dad1d9f6
Fixed testbench_fp to use modified unpacker
2024-05-12 12:11:48 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
David Harris
c0743a1fcf
Added missing convert F to/from Int64 tests for arch64f
2024-05-11 02:29:47 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df
Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1.
2024-05-10 08:51:59 -05:00
David Harris
66b33c09be
Added Zaamo and Zalrsc support to testbench and regression
2024-05-10 05:41:00 -07:00
David Harris
54750ae4d5
Fixed out-of-bound vector accesses in testbench_fp when FLEN < Q_LEN
2024-05-09 19:52:37 -07:00
David Harris
bdd0043cd1
Testbench terminates buildroot sim at instruction limit
2024-05-09 07:58:53 -07:00
David Harris
47af54b131
Fixed buildroot prematurely terminating in VCS
2024-05-09 07:29:45 -07:00
David Harris
0d1d59a3d8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-08 18:58:01 -07:00
Divya2030
31ae18922b
regression_wally vcs run works
2024-05-08 04:25:03 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
Divya2030
a3f1a274d2
VCS Simulation Passed
2024-05-07 10:41:02 -07:00
David Harris
06d3591a15
Divy's change for VCS signature checking
2024-05-04 02:45:43 -07:00
Divya2030
12a9c0ebd6
pmp coverage
2024-05-02 11:53:32 -07:00
Divya2030
ee566aa856
pmp coverage
2024-05-02 11:53:04 -07:00
Divya2030
7a5eac963e
Revert "pmp functional coverage basic"
...
This reverts commit db2b07b05d
2024-05-02 11:43:33 -07:00
Divya2030
3853f94337
Revert "initial commit pmp basic coverage working"
...
This reverts commit 7ca1c976c0
2024-05-02 11:23:59 -07:00
Divya2030
9f27f3fe28
Merge branch 'main' of github.com:Divya2030/cvw
2024-05-02 11:21:05 -07:00
Divya2030
db2b07b05d
pmp functional coverage basic
2024-05-02 11:20:03 -07:00
Divya2030
694c69c651
Merge branch 'openhwgroup:main' into main
2024-05-02 10:34:15 -07:00
Divya2030
7ca1c976c0
initial commit pmp basic coverage working
2024-05-02 10:33:29 -07:00
David Harris
e667adf946
Added covergen directed coverage generator
2024-05-01 14:47:37 -07:00
David Harris
9b22275438
Removed unused signals from WallyTracer
2024-04-30 08:54:28 -07:00
David Harris
fc7c183d56
Added fcvtmod.w.d_b22 to regression now that it works in Sail
2024-04-29 17:52:21 -07:00
David Harris
160c11d786
Integrating riscv-dv coverage
2024-04-24 10:17:49 -07:00
David Harris
6415bfc3c2
Code and testbench cleanup
2024-04-23 10:17:44 -07:00
David Harris
f9eec8c43f
Merged wsim changes
2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493
Add support for dumping vcd.
2024-04-22 13:03:51 -07:00
David Harris
26711083df
Flushing uart.out file to observe progress
2024-04-21 20:08:35 -07:00
David Harris
03f49dea3f
regression printing improvements
2024-04-21 19:45:09 -07:00
David Harris
be15a11622
Fixed conflicts on getenv
2024-04-21 08:38:13 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
1817ab2e11
testbench import is happy now for Questa, but throws lint warning for VCS
2024-04-20 23:13:13 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
338f37b570
Moved getenv/getenvval declaration to config-shared so lint and regression both run
2024-04-20 17:19:42 -07:00
David Harris
571b67f565
Merging PR738
2024-04-20 17:15:17 -07:00
slmnemo
f0229e970b
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
2024-04-20 17:07:54 -07:00
slmnemo
66a002d879
Removed unused rmCmd string declaration
2024-04-20 16:58:23 -07:00
slmnemo
354d447269
Changed testbench to use fopen instead of opening and closing uartfile whenever writing
2024-04-20 16:56:54 -07:00
David Harris
d9ebfdfc4f
Enabled Zcb tests
2024-04-20 13:16:54 -07:00
Quswar Abid
1b18568d87
the fix Rose provided in meeting
2024-04-17 09:39:21 -07:00
Kunlin Han
29c19d9cb4
Add system function through DPI to avoid missing support in Verilator.
2024-04-16 11:23:00 -07:00
Rose Thompson
1eb1beed95
Fixed merge conflict bug in the last pull request.
2024-04-16 10:32:24 -05:00
Rose Thompson
9fe86712d8
Merge branch 'main' into wsim_verilator
2024-04-16 09:07:50 -05:00
David Harris
160162c98a
Merge pull request #728 from Karl-Han/verilator_getenv
...
Add support for getenvval as wrapper for Verilator's getenv
2024-04-15 17:55:34 -06:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
slmnemo
342c99d6ea
Rearranged uart_logger block to only generate if UART is supported
2024-04-12 21:30:33 -07:00
Kunlin Han
eeb5c59143
Remove unnecessary sig and avoid uninitialized signal inside always block.
2024-04-12 16:06:10 -07:00
Kunlin Han
4d9de94029
Add support for getenvval as wrapper for Verilator's getenv.
2024-04-12 14:59:04 -07:00
David Harris
60e70c1986
Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.
2024-04-08 05:57:18 -07:00
David Harris
d182a2925e
Fixed bug in testbench_fp for XLEN > FLEN
2024-04-07 05:40:18 -07:00
Rose Thompson
bb072fba84
Fixed the buildroot issue.
2024-04-06 18:25:53 -05:00
Rose Thompson
46fdfde7ec
Removed unnecessary display from testbench.
2024-04-06 16:10:18 -05:00
Rose Thompson
8885c32f7c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-04-06 15:55:00 -05:00
David Harris
e8111da88a
Removed unused old regression-wally
2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e
Added GUI support and removed unused wave files
2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90
Passing arguments to buildroot, not yet checking result correctly
2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f
Working on buildroot in regression
2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
David Harris
9ee7544d3c
TestFloat running; normal testbench broken
2024-04-06 09:28:07 -07:00
David Harris
4b19f6d542
testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./
2024-04-06 08:22:39 -07:00
slmnemo
d107a42e8c
Replaced rewrite command with system rm command for uart file. Fixed comment on line 573
2024-04-05 21:39:41 -07:00
slmnemo
2fcae601a9
Replaced funky rewrite call with file removal
2024-04-05 20:59:08 -07:00
David Harris
7b56809323
wsim runs a Questa sim
2024-04-05 19:08:14 -07:00
slmnemo
3ee25c8936
Merged testbench changes
2024-04-05 17:20:03 -07:00
slmnemo
5378b61eb2
Added UART output file buildroot_uart.out for Linux test 'buildroot'.
2024-04-05 17:18:03 -07:00
Rose Thompson
23e51e7277
starting on functional coverage for fence.i.
2024-04-04 15:44:57 -05:00
David Harris
ccd0e9cd0c
Clean up testbench-fp for Verilator
2024-04-03 17:26:41 -07:00
David Harris
ae8d581f4e
Started implementing Verilator for testfloat
2024-04-03 17:09:19 -07:00
Divya2030
aa6eacbce5
Merge branch 'openhwgroup:main' into main
2024-04-03 10:40:30 -07:00
Divya2030
135f3b6f8f
vcs testbench
2024-04-03 10:39:02 -07:00
David Harris
8755966f50
Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved
2024-04-03 07:23:02 -07:00
David Harris
8741b01818
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-03 06:51:24 -07:00
David Harris
929eb0430c
Testbench uses posedge control signals to speed up Verilator
2024-04-03 06:51:18 -07:00
Rose Thompson
c11d7ea55e
Fixed bug in the testbench which did not allow external memory to work correctly.
2024-04-01 10:59:40 -05:00
Rose Thompson
4a7c16990f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-28 13:45:12 -05:00
Rose Thompson
35eba468f7
Removed unused testbench-xcelium.sv.
2024-03-28 13:43:26 -05:00
Rose Thompson
b87cdd49a3
Merge pull request #690 from davidharrishmc/dev
...
fcvt.h.l fixes, removed delays
2024-03-28 13:42:41 -05:00
Rose Thompson
081cf5be55
Fixed the CacheHit logger bug.
2024-03-28 13:40:01 -05:00
David Harris
4eb7de7381
Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test
2024-03-26 13:58:59 -07:00
David Harris
0caab3c0c9
Removed delays from cacheLRU and testbench
2024-03-25 12:20:25 -07:00
David Harris
690338b758
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
2024-03-25 06:08:27 -07:00
Jordan Carlin
d580d7af5d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-23 17:56:23 -07:00
Jordan Carlin
fd97108dc3
Update testbench-fp to support Zfa in FPU modules
2024-03-23 17:55:59 -07:00
David Harris
bae52cf13d
Merge pull request #678 from Karl-Han/latest
...
[Resolved Conflict] Remove all #delay from non-testbench
2024-03-23 15:18:04 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
David Harris
b4a914a6e3
Commented out fcvt.h.l tests that don't run on fh_arch64gc arch64zfh; added testbench feature to print when the program jumps to address 0, presumably a bad trap handler
2024-03-14 21:53:30 -07:00
David Harris
9ff9f9e0ae
Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
2024-03-14 19:03:57 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
9a1fdba077
Added more Zbkb tests shared with Zbb
2024-03-10 22:24:16 -07:00
David Harris
2580d37fc0
ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder
2024-03-10 22:03:57 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
Rose Thompson
e870e8137b
Finished Wally rvvi tracer.
2024-03-08 09:16:30 -06:00
Rose Thompson
24dffa39d5
Yay. David and I got our first Quad load/store instructions working!
2024-03-07 12:48:52 -06:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
David Harris
9ba35991e3
Finished FPU coverage
2024-02-15 20:01:28 -08:00
Rose Thompson
6921bb265a
Removed old testbenches.
2024-02-07 16:04:28 -06:00
Rose Thompson
83dc9cd926
More cleanup.
2024-02-07 15:53:40 -06:00
Rose Thompson
0d008c9281
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
Plus major cleanup of wally-batch.do
2024-02-07 15:44:38 -06:00
Rose Thompson
2acbc95b72
Partially got linux imperas boot working in the main testbench.
2024-02-07 15:38:18 -06:00
Rose Thompson
7f3877f076
Finally have buildroot running in the main testbench!
2024-02-07 11:23:46 -06:00
David Harris
e7364290e3
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
2024-02-07 06:27:53 -08:00
David Harris
5bde0db64b
Added ZFH FMA tests from https://github.com/riscv-non-isa/riscv-arch-test/pull/367
2024-02-07 04:55:29 -08:00
Rose Thompson
812c169132
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-02-06 22:07:09 -06:00
Rose Thompson
5ab88a5daa
Updated to simplify configOptions.
2024-02-06 22:07:06 -06:00
David Harris
d71efedab5
Merge pull request #619 from ross144/main
...
Merged all regression tests except imperas linux boot into testbench.sv.
2024-02-06 16:19:42 -08:00
Rose Thompson
da65928f04
Fixed issue with branch deriv configs.
2024-02-06 16:07:41 -06:00
David Harris
dfee790ad7
Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet.
2024-02-06 12:35:56 -08:00
Rose Thompson
58580445ab
Only output instruction count when the csrs are implemented.
2024-02-05 14:42:27 -06:00
Rose Thompson
8b5970fdc4
Buildroot now reports every 100K instructions as before.
2024-02-05 13:19:48 -06:00
Rose Thompson
c9176f108e
Fixed paths to buildroot objdump label and addr files.
2024-02-05 13:09:31 -06:00
Rose Thompson
17380a68d5
Moved buildroot testbench to the main testbench.
...
However I don't have a positive control or negative indicator to
say when the test completes or passes.
2024-02-05 13:03:48 -06:00
Rose Thompson
44e87f3e3e
First cut at removing the linux testbench and merging build root into the main testbench.
2024-02-05 12:46:14 -06:00
David Harris
66c1c71a56
Coverage improvements
2024-02-04 18:56:40 -08:00
David Harris
4e376680be
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-02-04 09:34:48 -08:00
Jordan Carlin
0312476fb3
Update tlb camline ASID coverage to use single file
2024-02-03 09:48:57 -08:00
David Harris
fd5e492b2a
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-02-01 20:47:20 -08:00
Jordan Carlin
8633f263a2
Complete coverage of tlb camlines in IFU
2024-02-01 20:41:05 -08:00
David Harris
efdc571f59
Removed redundant assertion
2024-02-01 20:14:40 -08:00
Rose Thompson
d59daf9a6f
Fixed odd bug in the testbench which wasn't skipping signature check for coverage tests.
2024-02-01 12:22:28 -06:00
David Harris
49714cb282
Fixed assertions to throw fatal error, improved nightly regression to have passing cases
2024-01-31 21:39:18 -08:00
David Harris
111f592613
factor divsqrt out of floating-point test cases to run on more derived configs
2024-01-31 14:52:15 -08:00
David Harris
bf7e20e846
IEEE754 derivatives for testfloat
2024-01-30 09:49:27 -08:00
James E. Stine
0d9e2fdf60
update Boolean logic for all testing for divide
2024-01-29 17:37:35 -06:00
James E. Stine
95a97faf3f
Fixes testbench issues in testing against all vectors. Still a bug in ui32_to_f16_rz.sv - but will fix. Some things can be optimized. Overall, adds a FSM to test things more effectively. Actually is faster than previously as it assumed everything took the same number of cycles. Again, some things can be optimized
2024-01-29 16:46:34 -06:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
