mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Partially got linux imperas boot working in the main testbench.
This commit is contained in:
Rose Thompson
parent
d82ee04533
commit
2acbc95b72
@ -3,8 +3,8 @@
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#export RISCV=/scratch/moore/RISCV
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export IMPERAS_TOOLS=$(pwd)/imperas.ic
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export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
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export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
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#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
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export OTHERFLAGS=""
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#export OTHERFLAGS=""
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vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"
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vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
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@ -33,6 +33,9 @@ mkdir -p cov
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# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
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# variables and compacts into a single list for passing to vopt.
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set coverage 0
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set CoverageVoptArg ""
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set CoverageVsimArg ""
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set configOptions ""
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set from 4
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set step 1
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@ -47,6 +50,8 @@ for {set i 0} true {incr i} {
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if {$argc >= 3} {
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if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
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set coverage 1
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set CoverageVoptArg "+cover=sbecf"
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set CoverageVsimArg "-coverage"
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} elseif {$3 eq "configOptions"} {
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set configOptions $lst
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puts $configOptions
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@ -66,8 +71,9 @@ vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/der
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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if {$coverage} {
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# vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage
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puts "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt ${CoverageVoptArg}
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
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} else {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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@ -80,6 +86,7 @@ run -all
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if {$coverage} {
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puts "???????????????????????????"
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echo "Saving coverage to ${1}_${2}.ucdb"
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
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@ -32,25 +32,10 @@ vlib work
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
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#-- Run the Simulation
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#run -all
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run 7000 ms
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add log -recursive /*
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do linux-wave.do
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run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "buildroot-no-trace"} {
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if {$2 eq "buildroot"} {
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vlog -lint -work work_${1}_${2} \
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+define+USE_IMPERAS_DV \
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+incdir+../config/$1 \
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+incdir+../config/deriv/$1 \
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+incdir+../config/shared \
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+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
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+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
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@ -64,7 +49,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
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../src/cvw.sv \
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../testbench/testbench-linux-imperas.sv \
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../testbench/testbench.sv \
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../testbench/common/*.sv ../src/*/*.sv \
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../src/*/*/*.sv -suppress 2583
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@ -75,8 +60,8 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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# vsim -fprofile+perf
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# visualizer -fprofile+perf+dir=fprofile
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#
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eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
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-G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
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eval vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
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-G INSTR_LIMIT=1000000 -G TEST=$2 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
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eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \
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-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
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$env(OTHERFLAGS)
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@ -88,68 +73,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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#run 100 ns
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#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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run 9800 ms
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add log -recursive /testbench/dut/*
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do wave.do
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run 9800 ms
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run 200 ms
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#run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "fpga"} {
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echo "hello"
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vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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do fpga-wave.do
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add log -r /*
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run 20 ms
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} else {
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if {$2 eq "ahb"} {
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vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
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} else {
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# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
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vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
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}
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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view wave
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#-- display input and output signals as hexidecimal values
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#do ./wave-dos/peripheral-waves.do
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add log -recursive /*
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do wave.do
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#do wave-bus.do
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# power add generates the logging necessary for saif generation.
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#power add -r /dut/core/*
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#-- Run the Simulation
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run -all
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#power off -r /dut/core/*
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#power report -all -bsaif power.saif
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noview ../testbench/testbench.sv
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view wave
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}
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#elseif {$2 eq "buildroot-no-trace""} {
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# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
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# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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# run 100 ns
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# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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# add log -recursive /*
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# do linux-wave.do
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# run -all
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# exec ./slack-notifier/slack-notifier.py
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#}
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@ -29,6 +29,10 @@
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`include "tests.vh"
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`include "BranchPredictorType.vh"
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`ifdef USE_IMPERAS_DV
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`include "idv/idv.svh"
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`endif
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import cvw::*;
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module testbench;
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@ -43,6 +47,12 @@ module testbench;
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parameter RISCV_DIR = "/opt/riscv";
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parameter INSTR_LIMIT = 0;
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`ifdef USE_IMPERAS_DV
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import idvPkg::*;
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import rvviApiPkg::*;
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import idvApiPkg::*;
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`endif
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`include "parameter-defs.vh"
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logic clk;
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@ -547,8 +557,165 @@ module testbench;
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if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
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if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// ImperasDV Co-simulator hooks
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////////////////////////////////////////////////////////////////////////////////
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`ifdef USE_IMPERAS_DV
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rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
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wallyTracer #(P) wallyTracer(rvvi);
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trace2log idv_trace2log(rvvi);
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// trace2cov idv_trace2cov(rvvi);
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// enabling of comparison types
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trace2api #(.CMP_PC (1),
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.CMP_INS (1),
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.CMP_GPR (1),
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.CMP_FPR (1),
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.CMP_VR (0),
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.CMP_CSR (1)
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) idv_trace2api(rvvi);
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initial begin
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int iter;
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#1;
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IDV_MAX_ERRORS = 3;
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// Initialize REF (do this before initializing the DUT)
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if (!rvviVersionCheck(RVVI_API_VERSION)) begin
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$display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
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$fatal;
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end
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void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org"));
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void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv"));
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void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"));
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void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
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void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
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if (!rvviRefInit("")) begin
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$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
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$fatal;
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end
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// Volatile CSRs
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void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE
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void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE
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void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET
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void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET
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void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME
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// User HPMCOUNTER3 - HPMCOUNTER31
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for (iter='hC03; iter<='hC1F; iter++) begin
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void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx
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end
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// Machine MHPMCOUNTER3 - MHPMCOUNTER31
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for (iter='hB03; iter<='hB1F; iter++) begin
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void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx
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end
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// cannot predict this register due to latency between
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// pending and taken
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void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP
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void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP
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// Privileges for PMA are set in the imperas.ic
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// volatile (IO) regions are defined here
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// only real ROM/RAM areas are BOOTROM and UNCORE_RAM
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if (P.CLINT_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
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end
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if (P.GPIO_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
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end
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if (P.UART_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
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end
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if (P.PLIC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
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end
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if (P.SDC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
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end
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if (P.SPI_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE)));
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end
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if(P.XLEN==32) begin
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void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
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void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
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void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
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void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH
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end
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void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
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// Load memory
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begin
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longint x64;
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int x32[2];
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longint index;
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string memfilenameImperasDV, bootmemfilenameImperasDV;
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memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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$display("RVVI Loading bootmem.bin");
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memFile = $fopen(bootmemfilenameImperasDV, "rb");
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index = 'h1000 - 8;
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while(!$feof(memFile)) begin
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index+=8;
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readResult = $fread(x64, memFile);
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if (x64 == 0) continue;
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x32[0] = x64 & 'hffffffff;
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x32[1] = x64 >> 32;
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rvviRefMemoryWrite(0, index+0, x32[0], 4);
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rvviRefMemoryWrite(0, index+4, x32[1], 4);
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//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
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end
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$fclose(memFile);
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$display("RVVI Loading ram.bin");
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memFile = $fopen(memfilenameImperasDV, "rb");
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index = 'h80000000 - 8;
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while(!$feof(memFile)) begin
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index+=8;
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readResult = $fread(x64, memFile);
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if (x64 == 0) continue;
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x32[0] = x64 & 'hffffffff;
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x32[1] = x64 >> 32;
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rvviRefMemoryWrite(0, index+0, x32[0], 4);
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rvviRefMemoryWrite(0, index+4, x32[1], 4);
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//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
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end
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$fclose(memFile);
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$display("RVVI Loading Complete");
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void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address
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end
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end
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
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always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
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final begin
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void'(rvviRefShutdown());
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end
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`endif
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////////////////////////////////////////////////////////////////////////////////
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// END of ImperasDV Co-simulator hooks
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////////////////////////////////////////////////////////////////////////////////
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task automatic CheckSignature;
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// This task must be declared inside this module as it needs access to parameter P. There is
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// no way to pass P to the task unless we convert it to a module.
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