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1939 Commits

Author SHA1 Message Date
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
kipmacsaigoren
c2f4b49b15 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
687703f0d8 removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
7536e0a2ee Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
David Harris
4aeadaacf0 moved coemark and testsBP to tests 2021-10-20 09:10:06 -07:00
David Harris
0e4f6392d6 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00
David Harris
8747791bb8 radix 2 SRT checkin 2021-10-19 14:08:16 -07:00
James E. Stine
ed179b0bd9 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040 Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
df0b65e483 replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
d0b9ebd2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
d895fd7ee5 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825 Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
395e070917 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
886a650da4 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
d783acbbc5 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
09f51871c5 lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
4ea56ac68b some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Ross Thompson
5fdac9fa3b Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
c90d129498 Fixed boot loader program to start at correct address. 
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
 2021-10-11 17:22:23 -05:00
Shreya Sanghai
51185478df made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
f9b37c3ce1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
062fbfb610 Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
324230e2f9 added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
Ross Thompson
cbf4e76d1c Fixed sdc byte and nibble orders. 2021-10-11 12:15:52 -05:00
Ross Thompson
2e0dcaaff9 Fpga simualtion files. 2021-10-11 10:24:40 -05:00
Ross Thompson
3d9d4cc03f Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
8a64675b02 intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
a8ce4568aa Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
50e5b0a8f4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857 make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
266c706804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
2d09994a91 Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
644af40855 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
179223bef0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
5a987cf0ca use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1 FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
bbracker
54e0e8eb5b make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
kipmacsaigoren
086e6d130a rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
8e35701103 Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
381a8fcd27 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
Kip Macsai-Goren
3623dfa51e removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
3103b78493 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
David Harris
7e340d16fd moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
626780381a Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
bbracker
64a3043a88 update wave-do 2021-10-07 19:16:52 -04:00
bbracker
6e75f82589 update linux wave-do 2021-10-07 19:15:11 -04:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
0c408a9816 update scripts 2021-10-07 15:14:54 -05:00
bbracker
d45b8fa4dc more checkpoint reformatting 2021-10-07 04:27:45 -04:00
bbracker
a9052cb455 don't log rf[0] to checkpoint 2021-10-07 00:58:33 -04:00
bbracker
ec1e04e8b8 update linker scripts to look for vmlinux files 2021-10-06 16:55:38 -04:00
bbracker
1a1c4f28f4 update linker scripts to look for vmlinux files 2021-10-06 16:51:31 -04:00
James E. Stine
4dcfcfacfc TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
739e17ddac Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
kipmacsaigoren
086a0234ba Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
4ece7b5341 Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Skylar Litz
a924e79e26 added delayed MIP signal 2021-10-04 18:23:31 -04:00
kipmacsaigoren
4a9dd49785 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
Ross Thompson
e4e353c186 updated fpga wavefile. 2021-10-03 12:14:22 -05:00
Ross Thompson
4c81d3453e Added fpga wave file. 2021-10-03 11:56:11 -05:00
Ross Thompson
c10261f0ad Added more debug flags. 2021-10-03 11:41:21 -05:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
a15068717b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:43:47 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
07ff0940a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
a202c705cd checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
Ross Thompson
ec4a07de64 Movied tristate to test bench level. 2021-09-30 11:27:42 -05:00
Ross Thompson
db18aac9af Partially sd card read on fpga. 2021-09-30 11:23:09 -05:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
a47448c4d0 first attemtpt at checkpoint infrastructure 2021-09-28 22:33:47 -04:00
Ross Thompson
99070127d8 Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
bbracker
2ffdbdf6d2 condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
Ross Thompson
f2c1ca4bd5 added support to due partial fpga simulation. 2021-09-26 15:00:00 -05:00
Ross Thompson
6ac96db20b Merge branch 'main' into fpga 2021-09-26 13:22:53 -05:00
Ross Thompson
6dc25e07c2 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 
the flash card to dram.
Fixed latch issue in the sd card reader.
 2021-09-26 13:22:23 -05:00
Ross Thompson
55f3c15302 Merge branch 'sdc' into fpga 2021-09-25 19:33:07 -05:00
Ross Thompson
5bdd6a9d0c Almost done writting driver for flash card reader. 2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872 We now have a rough sdc read routine. 2021-09-25 17:51:38 -05:00
Ross Thompson
dd9fe60b28 Write of the SDC address register is correct. The command register is not yet working. 
The root problem is the command register needs to be reset at the end of the SDC transaction.
 2021-09-24 18:48:11 -05:00
Ross Thompson
5663522a3f Now have software interacting with the initialization and settting the address register. 2021-09-24 18:30:26 -05:00
Ross Thompson
232d4a554f Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
71e20c7f61 Fixed lint errors in the SDC. 2021-09-24 12:38:48 -05:00
Ross Thompson
0f87f68b9d Added either the sdModel or constant driver for the SDC ports in all test benches. 2021-09-24 12:31:51 -05:00
Ross Thompson
af28cfb70c Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
Ross Thompson
0a33f5fa46 setup so the sdc does not need to load a model in the imperas test bench. 2021-09-24 11:30:52 -05:00
Ross Thompson
78028947bf Updated Imperas test bench to work with the SDC reader. 2021-09-24 11:22:54 -05:00
Ross Thompson
4256ef82b1 SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
Ross Thompson
a182263b1c Added clock gater and divider to generate the SDCCLK. 2021-09-23 17:58:50 -05:00
Ross Thompson
9ed7a1f494 Partial implementation of SDC AHBLite interface. 2021-09-23 17:45:45 -05:00
Ross Thompson
0f7be5e591 Started the AHBLite to SDC interface. 2021-09-22 18:08:38 -05:00
bbracker
441759b81c switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
bbracker
b1c2a77fc2 update setup scripts to new testvector files 2021-09-22 12:31:10 -04:00
Ross Thompson
d4f514010d Changes to make fpga synthesizable. 
Added preload to test simple program on wally in fpga.
 2021-09-22 10:54:13 -05:00
Ross Thompson
f5905f33d3 Initial SD Card reader. 2021-09-22 10:50:29 -05:00
kipmacsaigoren
afd73ddada Merge branch 'ppa' into main 2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267 more input changes on prioirty thermometer. passes lint 2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2 added new fun ways of putting inputs into the priority thermometer 2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858 fix regression 2021-09-15 17:30:59 -04:00
kipmacsaigoren
437f2d5814 changed priority circuits for synthesis and light cleanup 2021-09-15 12:24:24 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
bbracker
f94a13e242 created script to determine which functions are most frequently used 2021-09-14 19:41:05 -04:00
David Harris
e32ab128e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
654f3d1940 Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
e98a046f9d Merge branch 'main' into fpga 2021-09-13 09:45:59 -05:00
Ross Thompson
d4c87d17b2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
1847198da9 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
b2fe8eddc0 Restored old integer divider 2021-09-12 22:07:52 -04:00
Ross Thompson
144003cb41 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
1f6e4c71fc Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
6f9983628e Removed one more genout bit. 2021-09-11 18:42:47 -05:00
Ross Thompson
00b0e6a7aa Merge branch 'main' into fpga 2021-09-11 16:00:23 -05:00
Ross Thompson
759b45ca36 Added calibration input. 
fixed HRESP duplication.
 2021-09-11 15:59:27 -05:00
Ross Thompson
225657b8f9 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
3b12235954 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
3ff8d0095d Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
b04e00d196 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:49:27 -05:00
Ross Thompson
29efd1d222 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
230c794edd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea fixed some lint bugs. 2021-09-09 12:38:57 -05:00
bbracker
886e8125db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-09 13:22:31 -04:00
bbracker
83520aeb42 changed fix_mem to not use hardcoded file names 2021-09-09 13:22:24 -04:00
David Harris
cb624fe679 Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
a31828e925 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
8141a515bb Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6606eea27e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
5bc90ef32f Slight modification to wave file. 2021-09-08 10:40:46 -05:00
bbracker
5e9a39e755 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
b3f00f2682 make testbench successfully deactivate TimerIntM so as to create a nice pulse 2021-09-07 15:36:47 -04:00
Ross Thompson
150a73d6cf Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
bbracker
28fed18421 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
Ross Thompson
00f50184d8 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
bbracker
0646bf2b90 help in case a script is run accidentally 2021-09-06 16:23:45 -04:00
bbracker
a13b561759 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
bbracker
58d478eb23 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
bbracker
0004f647ec switching over to hopefully more consistent QEMU simulated clock 2021-09-04 19:43:39 -04:00
bbracker
6155716de4 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing 2021-09-04 19:41:55 -04:00
James E. Stine
5bc3569b0e Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
bbracker
4a938e493e output trace to linux-testvectors folder 2021-09-01 17:37:46 -04:00
Ross Thompson
5c2deab4e4 Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
7607adc951 FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
4b0344898b Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
2dff72d9e9 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
de9e234ffa Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
62d91e9ea1 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
cbb47956cb Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
b230d4daec Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
b3849d8abb Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
b5d6c4fb46 Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
939ff663a5 Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
d2b3b7345e Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
c48556836b Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
7139279e50 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
a99b5f648b partial dcache reorg. 2021-08-25 12:42:05 -05:00
Ross Thompson
699053bab0 Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00
David Harris
cb13e36d20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
cf1e458ccf simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
b7972eafeb Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
bb3e94d68a Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
f006655bdc Renamed output of qemu trace. 2021-08-22 22:56:34 -05:00
Ross Thompson
b6e2710f5d Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
696be3ff68 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
c0667f30bb Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
Ross Thompson
95f5ebaf30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
d3417e309b Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
facd4062d0 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
66ad510abf Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
4c8ea89f15 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
4eca94268c Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
15085448d7 Updated linux-wave.do to have cursors at the timer interrupt problem. 2021-08-13 17:29:37 -05:00
Ross Thompson
4f1f9d6e37 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
4f3f26c5cb Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
492b6f0ea4 Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
a1c26a16d6 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Katherine Parry
567260751a move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
272425c41f Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
618cc18903 Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
3b327c949f Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00
Ross Thompson
4dfe326761 Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
192392b524 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
d0afa397ba Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
74e5b60819 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
05a32508eb Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
21555c392f LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
467e24c05c Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
fda9985382 Finally past the CLINT issues. 2021-08-06 16:41:34 -05:00
Ross Thompson
839822d3b1 Now past the CLINT issues. 2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
722d298c35 Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. 2021-08-05 16:49:03 -05:00
Ross Thompson
b7fc737d93 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-30 17:57:13 -05:00
Ross Thompson
245e7014b3 Added some comments to linux testbench. 2021-07-30 17:57:03 -05:00
Ross Thompson
cd8a66353c Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Ross Thompson
89a7b38f79 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
 2021-07-30 14:00:51 -05:00
Ross Thompson
b9f8c25280 Created new linux test bench and parsing scripts. 2021-07-29 20:26:50 -05:00
Katherine Parry
d8ca70fc45 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Ross Thompson
c60a1fed69 Fixed bug which caused stores to take an extra clock cycle. 2021-07-26 12:22:53 -05:00
Ross Thompson
5b376b9846 Fixed bug with the compressed immediate generation. Several formats should zero extend. 2021-07-26 11:55:31 -05:00
Ross Thompson
ce29d0f00f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2021-07-26 11:55:00 -05:00
Ross Thompson
0291d987da Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Katherine Parry
8198e8162a fixed some fpu lint errors 2021-07-24 16:41:12 -04:00
Katherine Parry
85d240c2a5 fpu cleanup 2021-07-24 15:00:56 -04:00
Katherine Parry
67ab0b165c fpu cleanup 2021-07-24 14:59:57 -04:00
Kip Macsai-Goren
8823339aef added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
0653630d29 added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
f02d52ce50 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 15:16:01 -04:00
bbracker
d7edfb7a70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 14:00:52 -04:00
bbracker
71ef87bc55 testbench workaround for QEMU's SSTATUS XLEN bits 2021-07-23 14:00:44 -04:00
kipmacsaigoren
3bb6c8b32f Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe Removed LEVELx states from HPTW 2021-07-23 08:11:15 -04:00
Ross Thompson
00f798b37e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 19:42:32 -05:00
Ross Thompson
32ec457e09 Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
ee1eef3620 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
427063ee05 Minor unpacking cleanup 2021-07-22 17:52:37 -04:00
Ross Thompson
007812dbdc Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
00858cd401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 14:05:08 -05:00
Ross Thompson
936e034be9 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
David Harris
0822d46e97 Move Z sign swapping out of unpacker 2021-07-22 14:32:38 -04:00
David Harris
85aaa4c6d7 Move Z=0 mux out of unpacker. 2021-07-22 14:28:55 -04:00
David Harris
c04f40d6e5 Move Z=0 mux out of unpacker. 2021-07-22 14:22:28 -04:00
David Harris
625d925369 Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
David Harris
f4b45adf44 Simplify unpacker 2021-07-22 13:42:16 -04:00
David Harris
02f0c67e6f Simplify unpacker 2021-07-22 13:40:42 -04:00
David Harris
2f23ca2b77 Removed Assumed1 from FPU interface 2021-07-22 13:04:47 -04:00
David Harris
926ffc8a15 Simplified interface to fclassify and fsgn (fixed) 2021-07-22 12:33:38 -04:00
David Harris
ae29eaa98d Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3 Cleaned up icache and dcache. 2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622 fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
bbracker
cdcf419147 make address translator signals visible in waveview 2021-07-21 20:07:49 -04:00
bbracker
70ef670da1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824 replace physical address checking with virtual address checking because address translator is broken 2021-07-21 19:47:13 -04:00
bbracker
b48d179c37 hardcoded hack to fix missing STVEC vector 2021-07-21 19:34:57 -04:00
Ross Thompson
1e88784bd4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7 fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0 Added comment about better muxing. 2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb 4 way set associative is now working. 2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e59490d032 Fixed TLB parameterization and valid bit flop to correctly do instr page faults 2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
bbracker
e8b966c5d1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 13:04:11 -04:00
bbracker
f7a61a5c73 progress on recovering from QEMU's errors 2021-07-21 13:00:32 -04:00
Ross Thompson
39fc9278ba Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760 Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. 
Also forgot to include cacheLRU.sv file.
 2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
Ross Thompson
8d0a552b5b Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
bbracker
d6c93a50aa fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
bbracker
b5ceb6f7c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 15:04:13 -04:00
bbracker
945c8d496f commented out old hack that used hardcoded addresses 2021-07-20 15:03:55 -04:00
David Harris
62b3673027 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
20744883df flag for optional boottim 2021-07-20 14:46:37 -04:00
Ross Thompson
a042c356e1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-20 13:27:58 -05:00
Ross Thompson
bb5b5e71b1 Replaced FinalReadDataM with ReadDataM in dcache. 2021-07-20 13:27:29 -05:00
bbracker
7694342d4e ignore mhpmcounters because QEMU doesn't implement them 2021-07-20 13:37:52 -04:00
bbracker
761300afcd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 12:08:46 -04:00
David Harris
c117356432 Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
bbracker
3de8461f3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 05:40:49 -04:00
bbracker
c9775de3b2 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) 2021-07-20 05:40:39 -04:00
James E. Stine
b36d6fe1be slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
bbracker
5347a58192 major fixes to CSR checking 2021-07-20 00:22:07 -04:00
Ross Thompson
ae2371f2ce Added performance counters for dcache access and dcache miss. 2021-07-19 22:12:20 -05:00
Ross Thompson
07c47f0034 Restored TIM range. 2021-07-19 21:17:31 -05:00
bbracker
a01fea69dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 19:30:40 -04:00