mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
switch testbench-linux's interrupts from xcause to mip and improve warning messages
This commit is contained in:
bbracker
parent
b1c2a77fc2
commit
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@ -30,15 +30,13 @@
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6779000; // # of instructions at which to turn on waves in graphical sim
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*8700000; // # of instructions at which to turn on waves in graphical sim
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string ProgramAddrMapFile, ProgramLabelMapFile;
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////// DUT /////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset;
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logic [`AHBW-1:0] readDataExpected;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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@ -51,7 +49,6 @@ module testbench();
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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@ -73,6 +70,7 @@ module testbench();
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// Testbench Core
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integer warningCount = 0;
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integer errorCount = 0;
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integer MIPexpected;
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// P, Instr Checking
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logic [`XLEN-1:0] PCW;
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integer data_file_all;
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@ -85,7 +83,6 @@ module testbench();
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logic checkInstrW;
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//integer RegAdr;
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integer fault;
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logic TrapW;
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@ -129,18 +126,29 @@ module testbench();
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logic forcedInterrupt;
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integer NumCSRMIndex;
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integer NumCSRWIndex;
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integer NumCSRPostWIndex;
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// logic CurrentInterruptForce;
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integer NumCSRPostWIndex;
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logic [`XLEN-1:0] InstrCountW;
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// -----------
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// Error Macro
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// -----------
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// ------------
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// Error Macros
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// ------------
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`define ERROR \
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errorCount +=1; \
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$display("processed %0d instructions with %0d warnings", InstrCountW, warningCount); \
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$stop;
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`define CSRwarn(CSR) \
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begin \
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if(`DEBUG_TRACE > 0) begin \
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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end \
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if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
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$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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if(!`DontHaltOnCSRMisMatch) fault = 1; \
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end \
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end
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initial begin
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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InstrCountW = '0;
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@ -149,16 +157,12 @@ module testbench();
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force dut.hart.priv.ExtIntM = 0;
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end
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/* -----\/----- EXCLUDED -----\/-----
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initial begin
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CurrentInterruptForce = 1'b0;
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end
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-----/\----- EXCLUDED -----/\----- */
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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// trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW;
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// Additonal W stage registers
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flopenrc #(`XLEN) MemAdrWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.WriteDataM, WriteDataW);
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flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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@ -176,8 +180,9 @@ module testbench();
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// always check PC, instruction bits
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if (checkInstrM) begin
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// read 1 line of the trace file
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matchCount = $fgets(line, data_file_all);
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matchCount = $fgets(line, data_file_all);
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if(`DEBUG_TRACE > 1) $display("Time %t, line %x", $time, line);
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// extract PC, Instr
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matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM);
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//$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM);
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@ -213,21 +218,17 @@ module testbench();
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RegWriteM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
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MarkerIndex += 3;
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// parse memory address, read data, and/or write data
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// parse memory address, read data, and/or write data
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end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
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MemOpM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
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MarkerIndex += 4;
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// parse CSRs, because there are 1 or more CSRs after the CSR token
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// we check if the CSR token or the number of CSRs is greater than 0.
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// if so then we want to parse for a CSR.
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// parse CSRs, because there are 1 or more CSRs after the CSR token
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// we check if the CSR token or the number of CSRs is greater than 0.
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// if so then we want to parse for a CSR.
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end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
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if(ExpectedTokens[MarkerIndex] == "CSR") begin
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// all additional CSR's won't have this token.
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@ -235,30 +236,13 @@ module testbench();
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end
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matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
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MarkerIndex += 2;
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// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
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// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
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// the msb of xcause will be set.
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// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
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// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
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if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
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//what type?
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ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
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$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
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forcedInterrupt = 1;
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if(ExpectedIntType == 0) begin
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force dut.hart.priv.SwIntM = 1'b1;
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$display("Activate spoofed SwIntM");
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end else if(ExpectedIntType == 4) begin
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force dut.hart.priv.TimerIntM = 1'b1;
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$display("Activate spoofed TimeIntM");
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end else if(ExpectedIntType == 8) begin
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force dut.hart.priv.ExtIntM = 1'b1;
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$display("Activate spoofed ExtIntM");
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end else forcedInterrupt = 0;
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end
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// match MIP to QEMU's because interrupts are imprecise
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if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin
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$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
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MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
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force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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end
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NumCSRM++;
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end
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end
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@ -268,12 +252,10 @@ module testbench();
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
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end
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if(textM.substr(0,5) == "rdtime") begin
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$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
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//dut.hart.ieu.dp.regf.wd3
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end
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end // if (checkInstrM)
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end
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end
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// step 1: register expected state into the write back stage.
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@ -320,37 +302,16 @@ module testbench();
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ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
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end
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end
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// override on special conditions
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#1;
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// override on special conditions
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if(~dut.hart.StallW) begin
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if(textW.substr(0,5) == "rdtime") begin
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$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
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//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
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release dut.uncore.clint.clint.MTIME;
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//release dut.hart.ieu.dp.regf.wd3;
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end
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end
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
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release dut.hart.ieu.dp.ReadDataM;
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end
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// force interrupts to 0
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if (forcedInterrupt) begin
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forcedInterrupt = 0;
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if(ExpectedIntType == 0) begin
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force dut.hart.priv.SwIntM = 1'b0;
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$display("Deactivate spoofed SwIntM");
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end
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else if(ExpectedIntType == 4) begin
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force dut.hart.priv.TimerIntM = 1'b0;
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$display("Deactivate spoofed TimeIntM");
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end
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else if(ExpectedIntType == 8) begin
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force dut.hart.priv.ExtIntM = 1'b0;
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$display("Deactivate spoofed ExtIntM");
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end
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release dut.hart.ieu.dp.ReadDataM;
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end
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end
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end
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@ -368,197 +329,75 @@ module testbench();
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// check PCW
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fault = 0;
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if(PCW != ExpectedPCW) begin
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$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
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$display("%tns, %d instrs: PCW %016x does not equal ExpectedPCW: %016x", $time, InstrCountW, PCW, ExpectedPCW);
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fault = 1;
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end
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// check instruction value
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if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
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$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
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$display("%tns, %d instrs: InstrW %x does not equal ExpectedInstrW: %x", $time, InstrCountW, dut.hart.ifu.InstrW, ExpectedInstrW);
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fault = 1;
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end
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// check the number of instructions
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if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
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$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
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if(!`DontHaltOnCSRMisMatch) fault = 1;
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end
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#2; // delay 2 ns.
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if(`DEBUG_TRACE > 2) begin
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$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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end
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if (RegWriteW == "GPR") begin
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if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
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$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("%tns, %d instrs: Reg Write Address %02d does not equal expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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fault = 1;
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end
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if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
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$display("%tns, %d instrs: RF[%02d] %016x does not equal expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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fault = 1;
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end
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if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
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$display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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fault = 1;
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end
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end
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if (MemOpW.substr(0,2) == "Mem") begin
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if(`DEBUG_TRACE > 3) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
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// always check address
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if (MemAdrW != ExpectedMemAdrW) begin
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$display("MemAdrW: %016x does not equal expected value: %016x", MemAdrW, ExpectedMemAdrW);
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fault = 1;
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end
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// check read data
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if(MemOpW == "MemR" || MemOpW == "MemRW") begin
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if(`DEBUG_TRACE > 3) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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if (dut.hart.ieu.dp.ReadDataW != ExpectedMemReadDataW) begin
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$display("ReadDataW: %016x does not equal expected value: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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fault = 1;
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if(`DEBUG_TRACE > 3) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
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// always check address
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if (MemAdrW != ExpectedMemAdrW) begin
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$display("%tns, %d instrs: MemAdrW %016x does not equal expected value: %016x", $time, InstrCountW, MemAdrW, ExpectedMemAdrW);
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fault = 1;
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end
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// check read data
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if(MemOpW == "MemR" || MemOpW == "MemRW") begin
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if(`DEBUG_TRACE > 3) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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if (dut.hart.ieu.dp.ReadDataW != ExpectedMemReadDataW) begin
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$display("%tns, %d instrs: ReadDataW %016x does not equal expected value: %016x", $time, InstrCountW, dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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fault = 1;
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end
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// check write data
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end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
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if(`DEBUG_TRACE > 3) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
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if (WriteDataW != ExpectedMemWriteDataW) begin
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$display("%tns, %d instrs: WriteDataW %016x does not equal expected value: %016x", $time, InstrCountW, WriteDataW, ExpectedMemWriteDataW);
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fault = 1;
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end
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end
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end
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end
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// check write data
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else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
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if(`DEBUG_TRACE > 3) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
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if (WriteDataW != ExpectedMemWriteDataW) begin
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$display("WriteDataW: %016x does not equal expected value: %016x", WriteDataW, ExpectedMemWriteDataW);
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fault = 1;
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end
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end
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end
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// check csr
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//$display("%t, about to check csr, NumCSRW = %d", $time, NumCSRW);
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for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
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/* -----\/----- EXCLUDED -----\/-----
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if(`DEBUG_TRACE > 0) begin
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$display("%t, NumCSRPostWIndex = %d, Expected CSR: %s = %016x", $time, NumCSRPostWIndex, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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end
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-----/\----- EXCLUDED -----/\----- */
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": begin
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if(`DEBUG_TRACE > 0) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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end
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if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
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$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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if(!`DontHaltOnCSRMisMatch) fault = 1;
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end
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end
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"mstatus": begin
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if(`DEBUG_TRACE > 0) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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end
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if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin
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$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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if(!`DontHaltOnCSRMisMatch) fault = 1;
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end
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end
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"mtvec": begin
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if(`DEBUG_TRACE > 0) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mip": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mie": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mideleg": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"medeleg": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mepc": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mtval": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"sepc": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"scause": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"stvec": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"stval": begin
|
||||
if(`DEBUG_TRACE > 0) begin
|
||||
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
end
|
||||
if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
||||
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
||||
if(!`DontHaltOnCSRMisMatch) fault = 1;
|
||||
end
|
||||
end
|
||||
"mhartid": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
|
||||
"mstatus": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
|
||||
"mtvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
|
||||
"mip": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
|
||||
"mie": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
|
||||
"mideleg":`CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
|
||||
"medeleg": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
|
||||
"mepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
|
||||
"mtval": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
|
||||
"sepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
|
||||
"scause": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
|
||||
"stvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
|
||||
"stval": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
|
||||
endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
|
||||
end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++)
|
||||
if (fault == 1) begin `ERROR end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user