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Changed some flops to settable

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This commit is contained in:
David Harris 2021-10-18 17:05:29 -07:00
parent 965946cae3
commit 8d08ca6a1e
3 changed files with 14 additions and 2 deletions
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12
wally-pipelined/src/generic/flop.sv
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@ -81,6 +81,18 @@ module flopenr #(parameter WIDTH = 8) (
else if (en) q <= #1 d;
endmodule
// flop with enable, asynchronous set
module flopens #(parameter WIDTH = 8) (
input logic clk, set, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge set)
if (set) q <= #1 1;
else if (en) q <= #1 d;
endmodule
// flop with enable, asynchronous load
module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
input logic clk, load, en,

2
wally-pipelined/src/privileged/csrm.sv
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@ -137,7 +137,7 @@ module csrm #(parameter
else if (`BUILDROOT == 1)
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
else
flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTEREN_REGW);
flopens #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
endgenerate
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);

2
wally-pipelined/src/privileged/csrs.sv
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@ -100,7 +100,7 @@ module csrs #(parameter
else if (`BUILDROOT == 1)
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
else
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, SCOUNTEREN_REGW);
flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
if (`N_SUPPORTED) begin
logic WriteSEDELEGM, WriteSIDELEGM;
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);