David Harris 72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.		2021-09-15 13:14:00 -04:00
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bin	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
config	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
fpu-testfloat/FMA/tbgen	FMA cleanup	2021-08-28 10:53:35 -04:00
linux-testgen	created script to determine which functions are most frequently used	2021-09-14 19:41:05 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
src	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
testbench	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-13 12:41:07 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00