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Set associate icache working, but way 0 is never written.

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This commit is contained in:
Ross Thompson 2021-09-07 12:46:16 -05:00
parent 00f50184d8
commit 150a73d6cf
3 changed files with 24 additions and 10 deletions
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4
wally-pipelined/config/rv64ic/wally-config.vh
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@ -57,10 +57,10 @@
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 2048
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 1
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256

13
wally-pipelined/src/cache/icache.sv vendored
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@ -70,7 +70,7 @@ module icache
localparam OFFSETWIDTH = $clog2(BlockByteLength);
localparam integer PA_WIDTH = `PA_BITS - 2;
localparam integer NUMWAYS = 4;
localparam integer NUMWAYS = `ICACHE_NUMWAYS;
// Input signals to cache memory
@ -118,6 +118,8 @@ module icache
logic [OFFSETLEN-1:0] BasePAdrOffsetF;
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
// on spill we want to get the first 2 bytes of the next cache block.
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
@ -139,9 +141,9 @@ module icache
.reset,
.RAdr(RAdr),
.PAdr(PCTagF),
.WriteEnable(ICacheMemWriteEnable), // *** connect
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable('1),
.TagWriteEnable(ICacheMemWriteEnable), // *** connect
.TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable),
.ClearValid(1'b0),
@ -274,6 +276,8 @@ module icache
// truncate the offset from PCPF for memory address generation
assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
icachefsm #(.BLOCKLEN(BLOCKLEN))
controller(.clk,
.reset,
@ -293,7 +297,8 @@ module icache
.CntEn,
.CntReset,
.SelAdr,
.SavePC
.SavePC,
.LRUWriteEn
);
// For now, assume no writes to executable memory

17
wally-pipelined/src/cache/icachefsm.sv vendored
View File

@ -61,7 +61,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
output logic CntEn,
output logic CntReset,
output logic [1:0] SelAdr,
output logic SavePC
output logic SavePC,
output logic LRUWriteEn
);
// FSM states
@ -134,7 +135,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
ICacheReadEn = 1'b0;
SavePC = 1'b0;
ICacheStallF = 1'b1;
LRUWriteEn = 1'b0;
case (CurrState)
STATE_READY: begin
SelAdr = 2'b00;
@ -144,6 +145,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
end else if (hit & ~spill) begin
SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
NextState = STATE_CPU_BUSY;
SelAdr = 2'b01;
@ -153,7 +155,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
end else if (hit & spill) begin
spillSave = 1'b1;
SelAdr = 2'b10;
NextState = STATE_HIT_SPILL;
LRUWriteEn = 1'b1;
NextState = STATE_HIT_SPILL;
end else if (~hit & ~spill) begin
CntReset = 1'b1;
NextState = STATE_MISS_FETCH_WDV;
@ -209,6 +212,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
UnalignedSelect = 1'b1;
SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
NextState = STATE_CPU_BUSY_SPILL;
SelAdr = 2'b10;
@ -242,6 +247,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
//SelAdr = 2'b01;
ICacheReadEn = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
SelAdr = 2'b01;
NextState = STATE_CPU_BUSY;
@ -268,7 +274,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
end
STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
SelAdr = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
ICacheReadEn = 1'b1;
ICacheReadEn = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_MISS_SPILL_2;
end
STATE_MISS_SPILL_2: begin
@ -288,6 +295,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
UnalignedSelect = 1'b1;
SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
NextState = STATE_CPU_BUSY;
SelAdr = 2'b01;
@ -323,6 +331,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
UnalignedSelect = 1'b1;
SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
NextState = STATE_CPU_BUSY_SPILL;
SelAdr = 2'b10;