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Added debugging directives to system verilog.

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This commit is contained in:
Ross Thompson 2021-09-27 13:57:46 -05:00
parent f2c1ca4bd5
commit 99070127d8
20 changed files with 344 additions and 61 deletions
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2
wally-pipelined/config/buildroot/wally-config.vh
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@ -95,7 +95,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Bus Interface width
`define AHBW 64

2
wally-pipelined/config/busybear/wally-config.vh
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@ -98,7 +98,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Bus Interface width
`define AHBW 64

2
wally-pipelined/config/coremark/wally-config.vh
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@ -95,7 +95,7 @@
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Test modes

2
wally-pipelined/config/coremark_bare/wally-config.vh
View File

@ -99,7 +99,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Test modes

2
wally-pipelined/config/rv32ic/wally-config.vh
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@ -95,7 +95,7 @@
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h00000020
`define SDC_RANGE 34'h0000001F
// Bus Interface width
`define AHBW 32

2
wally-pipelined/config/rv32icfd/wally-config.vh
View File

@ -95,7 +95,7 @@
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h00000020
`define SDC_RANGE 34'h0000001F
// Bus Interface width
`define AHBW 32

2
wally-pipelined/config/rv64ic/wally-config.vh
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@ -99,7 +99,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Test modes

2
wally-pipelined/config/rv64icfd/wally-config.vh
View File

@ -96,7 +96,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Bus Interface width
`define AHBW 64

2
wally-pipelined/config/rv64imc/wally-config.vh
View File

@ -94,7 +94,7 @@
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b1
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h00000020
`define SDC_RANGE 56'h0000001F
// Test modes

2
wally-pipelined/regression/wally-pipelined-fpga.do
View File

@ -30,7 +30,7 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
0 {vlog +incdir+../config/rv64BP +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
0 {vlog +incdir+../config/rv64BP +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/common/*.sv ../src/*/*.sv ../src/wally/wallypipelinedsocwrapper.v -suppress 2583}
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation

31
wally-pipelined/src/privileged/csrm.sv
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@ -64,27 +64,28 @@ module csrm #(parameter
MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11),
MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
) (
input logic clk, reset,
input logic StallW,
input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW,
input logic clk, reset,
input logic StallW,
input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
// 64-bit registers in RV64, or two 32-bit registers in RV32
//output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
);
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW;
(* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;

32
wally-pipelined/src/privileged/csrs.sv
View File

@ -46,21 +46,22 @@ module csrs #(parameter
SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9)
) (
input logic clk, reset,
input logic StallW,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
input logic STATUS_TVM,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW,
input logic clk, reset,
input logic StallW,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
input logic STATUS_TVM,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
(* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW,
output logic [`XLEN-1:0] SATP_REGW,
input logic [11:0] SIP_REGW, SIE_REGW,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM
(* mark_debug = "true" *) input logic [11:0] SIP_REGW, SIE_REGW,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM
);
//logic [`XLEN-1:0] zero = 0;
@ -73,7 +74,8 @@ module csrs #(parameter
logic WriteSTVECM;
logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW;
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS) && ~StallW;
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC) && ~StallW;

16
wally-pipelined/src/privileged/trap.sv
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@ -28,14 +28,14 @@
module trap (
input logic clk, reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
input logic LoadPageFaultM, StorePageFaultM,
input logic mretM, sretM, uretM,
(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
(* mark_debug = "true" *) input logic LoadPageFaultM, StorePageFaultM,
(* mark_debug = "true" *) input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
@ -53,7 +53,7 @@ module trap (
);
logic MIntGlobalEnM, SIntGlobalEnM;
logic [11:0] PendingIntsM;
(* mark_debug = "true" *) logic [11:0] PendingIntsM;
//logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
logic Exception1M;

1
wally-pipelined/src/sdc/SDC.sv
View File

@ -140,6 +140,7 @@ module SDC
assign InitTrans = HREADY & HSELSDC & (HTRANS != 2'b00);
//assign RegRead = InitTrans & ~HWRITE;
// register resolve combo loop
flopr #(1) RegReadReg(HCLK, ~HRESETn, InitTrans & ~HWRITE, RegRead);
// AHBLite Spec has write data 1 cycle after write command
flopr #(1) RegWriteReg(HCLK, ~HRESETn, InitTrans & HWRITE, RegWrite);

2
wally-pipelined/src/sdc/sd_clk_fsm.sv
View File

@ -47,7 +47,7 @@ module sd_clk_fsm
logic [3:0] w_next_state;
logic [3:0] r_curr_state;
(* mark_debug = "true" *) logic [3:0] r_curr_state;
// clock selection

2
wally-pipelined/src/sdc/sd_cmd_fsm.sv
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@ -91,7 +91,7 @@ module sd_cmd_fsm
logic [4:0] w_next_state, r_curr_state;
(* mark_debug = "true" *) logic [4:0] w_next_state, r_curr_state;
logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
logic [31:0] w_redo_result, w_error_result;

2
wally-pipelined/src/sdc/sd_dat_fsm.sv
View File

@ -61,7 +61,7 @@ module sd_dat_fsm
input logic LIMIT_SD_TIMERS
);
logic [3:0] w_next_state, r_curr_state;
(* mark_debug = "true" *) logic [3:0] w_next_state, r_curr_state;
logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT)
logic r_error_crc16_fd_Q;

258
wally-pipelined/src/sdc/tb/ramdisk2.hex
View File

@ -1,3 +1,260 @@
@0000000 10 32 54 76
@0000004 00 01 02 03
@0000008 04 05 06 07
@000000C 08 09 0A 0B
@0000010 0C 0D 0E 0F
@0000014 0F 0E 0D 0C
@0000018 0B 0A 09 08
@000001C 07 06 05 04
@0000020 03 02 01 00
@0000024 10 32 54 76
@0000028 10 32 54 76
@000002C 10 32 54 76
@0000030 10 32 54 76
@0000034 10 32 54 76
@0000038 10 32 54 76
@000003C 10 32 54 76
@0000040 10 32 54 76
@0000044 10 32 54 76
@0000048 10 32 54 76
@000004C 10 32 54 76
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@0000054 10 32 54 76
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@000005C 10 32 54 76
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@000006C 10 32 54 76
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@000008C 10 32 54 76
@0000090 10 32 54 76
@0000094 10 32 54 76
@0000098 10 32 54 76
@000009C 10 32 54 76
@00000A0 10 32 54 76
@00000A4 10 32 54 76
@00000A8 10 32 54 76
@00000AC 10 32 54 76
@00000B0 10 32 54 76
@00000B4 10 32 54 76
@00000B8 10 32 54 76
@00000BC 10 32 54 76
@00000C0 10 32 54 76
@00000C4 10 32 54 76
@00000C8 10 32 54 76
@00000CC 10 32 54 76
@00000D0 10 32 54 76
@00000D4 10 32 54 76
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@00000DC 10 32 54 76
@00000E0 10 32 54 76
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@00000E8 10 32 54 76
@00000EC 10 32 54 76
@00000F0 10 32 54 76
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@00000F8 10 32 54 76
@00000FC 10 32 54 76
@0000100 10 32 54 76
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@000010C 10 32 54 76
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@0000114 10 32 54 76
@0000118 10 32 54 76
@000011C 10 32 54 76
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@0000128 10 32 54 76
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@00001AC 10 32 54 76
@00001B0 10 32 54 76
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@00001C0 10 32 54 76
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@00001C8 10 32 54 76
@00001CC 10 32 54 76
@00001D0 10 32 54 76
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@00001DC 10 32 54 76
@00001E0 10 32 54 76
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@00001EC 10 32 54 76
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@00001F8 10 32 54 76
@00001FC 10 32 54 76
@0000200 20 42 64 86
@0000204 30 52 74 96
@0000208 40 62 84 A6
@000020C 50 72 94 B6
@0000210 60 82 A4 C6
@0000214 70 92 B4 D6
@0000218 80 A2 C4 E6
@000021C 90 B2 D4 F6
@0000220 A0 C2 E4 06
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@0000228 C0 E2 04 26
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@00002C0 20 42 64 86
@00002C4 30 52 74 96
@00002C8 40 62 84 A6
@00002CC 50 72 94 B6
@00002D0 60 82 A4 C6
@00002D4 70 92 B4 D6
@00002D8 80 A2 C4 E6
@00002DC 90 B2 D4 F6
@00002E0 A0 C2 E4 06
@00002E4 B0 D2 F4 16
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@00002F0 E0 02 24 46
@00002F4 F0 12 34 56
@00002F8 00 22 44 66
@00002FC 10 32 54 76
@0000300 20 42 64 86
@0000304 30 52 74 96
@0000308 40 62 84 A6
@000030C 50 72 94 B6
@0000310 60 82 A4 C6
@0000314 70 92 B4 D6
@0000318 80 A2 C4 E6
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@0000320 A0 C2 E4 06
@0000324 B0 D2 F4 16
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@0000334 F0 12 34 56
@0000338 00 22 44 66
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@0000360 A0 C2 E4 06
@0000364 B0 D2 F4 16
@0000368 C0 E2 04 26
@000036C D0 F2 14 36
@0000370 E0 02 24 46
@0000374 F0 12 34 56
@0000378 00 22 44 66
@000037C 10 32 54 76
@0000380 20 42 64 86
@0000384 30 52 74 96
@0000388 40 62 84 A6
@000038C 50 72 94 B6
@0000390 60 82 A4 C6
@0000394 70 92 B4 D6
@0000398 80 A2 C4 E6
@000039C 90 B2 D4 F6
@00003A0 A0 C2 E4 06
@00003A4 B0 D2 F4 16
@00003A8 C0 E2 04 26
@00003AC D0 F2 14 36
@00003B0 E0 02 24 46
@00003B4 F0 12 34 56
@00003B8 00 22 44 66
@00003BC 10 32 54 76
@00003C0 20 42 64 86
@00003C4 30 52 74 96
@00003C8 40 62 84 A6
@00003CC 50 72 94 B6
@00003D0 60 82 A4 C6
@00003D4 70 92 B4 D6
@00003D8 80 A2 C4 E6
@00003DC 90 B2 D4 F6
@00003E0 A0 C2 E4 06
@00003E4 B0 D2 F4 16
@00003E8 C0 E2 04 26
@00003EC D0 F2 14 36
@00003F0 E0 02 24 46
@00003F4 F0 12 34 56
@00003F8 00 22 44 66
@00003FC 10 32 54 76
@20000000 10 32 54 76
@20000004 00 01 02 03
@20000008 04 05 06 07
@ -126,7 +383,6 @@
@200001F4 10 32 54 76
@200001F8 10 32 54 76
@200001FC 10 32 54 76
@20000200 20 42 64 86
@20000204 30 52 74 96
@20000208 40 62 84 A6

39
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -58,7 +58,8 @@ module wallypipelinedhart
// logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW;
logic RetM, TrapM;
logic RetM;
(* mark_debug = "true" *) logic TrapM;
// new signals that must connect through DP
logic MulDivE, W64E;
@ -69,14 +70,16 @@ module wallypipelinedhart
logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E;
// logic [31:0] InstrF;
logic [31:0] InstrD, InstrE, InstrM, InstrW;
logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE, PCLinkW;
logic [31:0] InstrD, InstrE, InstrW;
(* mark_debug = "true" *) logic [31:0] InstrM;
logic [`XLEN-1:0] PCD, PCE, PCLinkE, PCLinkW;
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic [1:0] MemRWE;
logic [1:0] MemRWM;
logic InstrValidM;
(* mark_debug = "true" *) logic [1:0] MemRWM;
(* mark_debug = "true" *) logic InstrValidM;
logic InstrMisalignedFaultM;
logic DataMisalignedM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
@ -133,8 +136,10 @@ module wallypipelinedhart
// cpu lsu interface
logic [2:0] Funct3M;
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
logic [`XLEN-1:0] ReadDataM;
logic [`XLEN-1:0] MemAdrE;
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
(* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM;
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
logic [`XLEN-1:0] ReadDataW;
logic CommittedM;
@ -277,6 +282,7 @@ module wallypipelinedhart
// presently stub out SetFlagsM and FRegWriteM
//assign SetFflagsM = 0;
//assign FRegWriteM = 0;
/* -----\/----- EXCLUDED -----\/-----
// ILA probe most important signals in CPU.
@ -287,6 +293,23 @@ module wallypipelinedhart
.probe3(ReadDataM),
.probe4(TrapM),
.probe5(MemRWM),
.probe6(InstrM));
.probe6(InstrM),
.probe7(InstrValidM),
.probe8({PendingIntsM, InstrMisalignedFaultM , InstrAccessFaultM , IllegalInstrFaultM ,
LoadMisalignedFaultM , StoreMisalignedFaultM ,
InstrPageFaultM , LoadPageFaultM , StorePageFaultM ,
BreakpointFaultM , EcallFaultM ,
LoadAccessFaultM , StoreAccessFaultM}),
.probe9(MEPC_REGW),
.probe10(MCAUSE_REGW),
.probe11(MTVAL_REGW),
.probe12(MIP_REGW),
.probe13(MIE_REGW),
.probe14(SIP_REGW),
.probe15(SIE_REGW),
.probe16({Match, SizeValid, Supported, AccessValid}));
-----/\----- EXCLUDED -----/\----- */
endmodule

2
wally-pipelined/testbench/testbench-fpga.sv
View File

@ -591,7 +591,7 @@ string tests32f[] = '{
.HRESPTim(HRESPEXT));
wallypipelinedsoc dut(.*);
wallypipelinedsocwrapper dut(.*);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,