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Lint cleaning, riscv-arch-test testing

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This commit is contained in:
David Harris 2021-09-09 11:05:12 -04:00
parent a31828e925
commit cb624fe679
10 changed files with 80 additions and 157 deletions
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5
wally-pipelined/regression/regression-wally.py
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@ -33,6 +33,11 @@ configs = [
cmd="vsim -do wally-buildroot-batch.do -c > {}",
grepstr="loaded 6000 instructions"
),
TestCase(
name="arch64",
cmd="vsim > {} -c <<!\ndo wally-arch.do ../config/rv64ic rv64ic\n!",
grepstr="All tests ran without failures"
),
TestCase(
name="rv32ic",
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv32ic rv32ic\n!",

3
wally-pipelined/regression/sim-wally-arch-batch Executable file
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@ -0,0 +1,3 @@
vsim -c <<!
do wally-arch.do ../config/rv64ic rv64ic
!

6
wally-pipelined/regression/wally-arch.do
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@ -17,10 +17,10 @@
onbreak {resume}
# create library
if [file exists work] {
if [file exists work-arch] {
vdel -all
}
vlib work
vlib work-arch
# compile source files
# suppress spurious warnngs about
@ -35,7 +35,7 @@ switch $argc {
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -o workopt
vopt +acc work-arch.testbench -o workopt
vsim workopt
view wave

6
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -46,11 +46,11 @@ module cachereplacementpolicy
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] <= '0;
ReplacementBits[index] = '0;
end else begin
BlockReplacementBits <= ReplacementBits[RAdr];
BlockReplacementBits = ReplacementBits[RAdr];
if (LRUWriteEn) begin
ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacement;
end
end
end

3
wally-pipelined/src/cache/cacheway.sv vendored
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@ -41,7 +41,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
input logic SetDirty,
input logic ClearDirty,
input logic SelEvict,
input logic VictimWay,
input logic VictimWay,
output logic [BLOCKLEN-1:0] ReadDataBlockWayMasked,
output logic WayHit,
@ -54,6 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [TAGLEN-1:0] ReadTag;
logic Valid;
logic Dirty;
logic SelectedWay; // dh: *** do ways need to have more than 1 bit?
genvar words;

2
wally-pipelined/src/cache/icache.sv vendored
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@ -142,7 +142,7 @@ module icache
.RAdr(RAdr),
.PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable('1),
.WriteWordEnable({{(BLOCKLEN/`XLEN)-1{1'b0}}, 1'b1}),
.TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable),

6
wally-pipelined/src/mmu/priorityonehot.sv
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@ -35,6 +35,8 @@ module priorityonehot #(parameter ENTRIES = 8) (
output logic [ENTRIES-1:0] y
);
/* verilator lint_off UNOPTFLAT */
logic [ENTRIES-1:0] nolower;
// generate thermometer code mask
@ -47,5 +49,7 @@ module priorityonehot #(parameter ENTRIES = 8) (
endgenerate
assign y = a & nolower;
/* verilator lint_on UNOPTFLAT */
endmodule

4
wally-pipelined/src/mmu/prioritythermometer.sv
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@ -30,11 +30,14 @@
`include "wally-config.vh"
/* verilator lint_off UNOPTFLAT */
module prioritythemometer #(parameter N = 8) (
input logic [N-1:0] a,
output logic [N-1:0] y
);
// generate thermometer code mask
genvar i;
generate
@ -47,4 +50,5 @@ module prioritythemometer #(parameter N = 8) (
endmodule
/* verilator lint_on UNOPTFLAT */

200
wally-pipelined/testbench/testbench-arch.sv
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@ -161,53 +161,55 @@ string tests32f[] = '{
};
string tests64m[] = '{
"rv64m/I-MUL-01", "3000",
"rv64m/I-MULH-01", "3000",
"rv64m/I-MULHSU-01", "3000",
"rv64m/I-MULHU-01", "3000",
"rv64m/I-MULW-01", "3000",
"rv64m/I-DIV-01", "3000",
"rv64m/I-DIVU-01", "3000",
"rv64m/I-DIVUW-01", "3000",
"rv64m/I-DIVW-01", "3000",
"rv64m/I-REM-01", "3000",
"rv64m/I-REMU-01", "3000",
"rv64m/I-REMUW-01", "3000",
"rv64m/I-REMW-01", "3000"
};
"rv64i_m/M/div-01", "9010",
"rv64i_m/M/divu-01", "a010",
"rv64i_m/M/divuw-01", "a010",
"rv64i_m/M/divw-01", "9010",
"rv64i_m/M/mul-01", "9010",
"rv64i_m/M/mulh-01", "9010",
"rv64i_m/M/mulhsu-01", "9010",
"rv64i_m/M/mulhu-01", "a010",
"rv64i_m/M/mulw-01", "9010",
"rv64i_m/M/rem-01", "9010",
"rv64i_m/M/remu-01", "a010",
"rv64i_m/M/remuw-01", "a010",
"rv64i_m/M/remw-01", "9010"
};
string tests64ic[] = '{
"rv64ic/I-C-ADD-01", "3000",
"rv64ic/I-C-ADDI-01", "3000",
"rv64ic/I-C-ADDIW-01", "3000",
"rv64ic/I-C-ADDW-01", "3000",
"rv64ic/I-C-AND-01", "3000",
"rv64ic/I-C-ANDI-01", "3000",
"rv64ic/I-C-BEQZ-01", "3000",
"rv64ic/I-C-BNEZ-01", "3000",
"rv64ic/I-C-EBREAK-01", "2000",
"rv64ic/I-C-J-01", "3000",
"rv64ic/I-C-JALR-01", "4000",
"rv64ic/I-C-JR-01", "4000",
"rv64ic/I-C-LD-01", "3420",
"rv64ic/I-C-LDSP-01", "3420",
"rv64ic/I-C-LI-01", "3000",
"rv64ic/I-C-LUI-01", "2000",
"rv64ic/I-C-LW-01", "3110",
"rv64ic/I-C-LWSP-01", "3110",
"rv64ic/I-C-MV-01", "3000",
"rv64ic/I-C-NOP-01", "2000",
"rv64ic/I-C-OR-01", "3000",
"rv64ic/I-C-SD-01", "3000",
"rv64ic/I-C-SDSP-01", "3000",
"rv64ic/I-C-SLLI-01", "3000",
"rv64ic/I-C-SRAI-01", "3000",
"rv64ic/I-C-SRLI-01", "3000",
"rv64ic/I-C-SUB-01", "3000",
"rv64ic/I-C-SUBW-01", "3000",
"rv64ic/I-C-SW-01", "3000",
"rv64ic/I-C-SWSP-01", "3000",
"rv64ic/I-C-XOR-01", "3000"
"rv64i_m/C/cadd-01", "8010",
"rv64i_m/C/caddi-01", "4010",
"rv64i_m/C/caddi16sp-01", "2010",
"rv64i_m/C/caddi4spn-01", "2010",
"rv64i_m/C/caddiw-01", "4010",
"rv64i_m/C/caddw-01", "8010",
"rv64i_m/C/cand-01", "8010",
"rv64i_m/C/candi-01", "4010",
"rv64i_m/C/cbeqz-01", "4010",
"rv64i_m/C/cbnez-01", "5010",
"rv64i_m/C/cebreak-01", "2070",
"rv64i_m/C/cj-01", "3010",
"rv64i_m/C/cjalr-01", "2010",
"rv64i_m/C/cjr-01", "2010",
"rv64i_m/C/cld-01", "2010",
"rv64i_m/C/cldsp-01", "2010",
"rv64i_m/C/cli-01", "2010",
"rv64i_m/C/clui-01", "2010",
"rv64i_m/C/clw-01", "2010",
"rv64i_m/C/clwsp-01", "2010",
"rv64i_m/C/cmv-01", "2010",
"rv64i_m/C/cnop-01", "2010",
"rv64i_m/C/cor-01", "8010",
"rv64i_m/C/csd-01", "3010",
"rv64i_m/C/csdsp-01", "3010",
"rv64i_m/C/cslli-01", "2010",
"rv64i_m/C/csrai-01", "2010",
"rv64i_m/C/csrli-01", "2010",
"rv64i_m/C/csub-01", "8010",
"rv64i_m/C/csubw-01", "8010",
"rv64i_m/C/csw-01", "3010",
"rv64i_m/C/cswsp-01", "3010",
"rv64i_m/C/cxor-01", "8010"
};
string tests64iNOc[] = {
@ -265,102 +267,6 @@ string tests32f[] = '{
"rv64i_m/I/sw-align-01", "3010",
"rv64i_m/I/xor-01", "9010",
"rv64i_m/I/xori-01", "6010"
/* //"rv64i/WALLY-PIPELINE-100K", "f7ff0",
"rv64i/I-ADD-01", "3000",
"rv64i/I-ADDI-01", "3000",
"rv64i/I-ADDIW-01", "3000",
"rv64i/I-ADDW-01", "3000",
"rv64i/I-AND-01", "3000",
"rv64i/I-ANDI-01", "3000",
"rv64i/I-AUIPC-01", "3000",
"rv64i/I-BEQ-01", "4000",
"rv64i/I-BGE-01", "4000",
"rv64i/I-BGEU-01", "4000",
"rv64i/I-BLT-01", "4000",
"rv64i/I-BLTU-01", "4000",
"rv64i/I-BNE-01", "4000",
"rv64i/I-DELAY_SLOTS-01", "2000",
"rv64i/I-EBREAK-01", "2000",
"rv64i/I-ECALL-01", "2000",
"rv64i/I-ENDIANESS-01", "2010",
"rv64i/I-IO-01", "2050",
"rv64i/I-JAL-01", "3000",
"rv64i/I-JALR-01", "4000",
"rv64i/I-LB-01", "4020",
"rv64i/I-LBU-01", "4020",
"rv64i/I-LD-01", "4420",
"rv64i/I-LH-01", "4050",
"rv64i/I-LHU-01", "4050",
"rv64i/I-LUI-01", "2000",
"rv64i/I-LW-01", "4110",
"rv64i/I-LWU-01", "4110",
"rv64i/I-MISALIGN_LDST-01", "2010",
"rv64i/I-NOP-01", "2000",
"rv64i/I-OR-01", "3000",
"rv64i/I-ORI-01", "3000",
"rv64i/I-RF_size-01", "2000",
"rv64i/I-RF_width-01", "2000",
"rv64i/I-RF_x0-01", "2010",
"rv64i/I-SB-01", "4000",
"rv64i/I-SD-01", "4000",
"rv64i/I-SH-01", "4000",
"rv64i/I-SLL-01", "3000",
"rv64i/I-SLLI-01", "3000",
"rv64i/I-SLLIW-01", "3000",
"rv64i/I-SLLW-01", "3000",
"rv64i/I-SLT-01", "3000",
"rv64i/I-SLTI-01", "3000",
"rv64i/I-SLTIU-01", "3000",
"rv64i/I-SLTU-01", "3000",
"rv64i/I-SRA-01", "3000",
"rv64i/I-SRAI-01", "3000",
"rv64i/I-SRAIW-01", "3000",
"rv64i/I-SRAW-01", "3000",
"rv64i/I-SRL-01", "3000",
"rv64i/I-SRLI-01", "3000",
"rv64i/I-SRLIW-01", "3000",
"rv64i/I-SRLW-01", "3000",
"rv64i/I-SUB-01", "3000",
"rv64i/I-SUBW-01", "3000",
"rv64i/I-SW-01", "4000",
"rv64i/I-XOR-01", "3000",
"rv64i/I-XORI-01", "3000",
"rv64i/WALLY-ADD", "4000",
"rv64i/WALLY-SUB", "4000",
"rv64i/WALLY-ADDI", "3000",
"rv64i/WALLY-ANDI", "3000",
"rv64i/WALLY-ORI", "3000",
"rv64i/WALLY-XORI", "3000",
"rv64i/WALLY-SLTI", "3000",
"rv64i/WALLY-SLTIU", "3000",
"rv64i/WALLY-SLLI", "3000",
"rv64i/WALLY-SRLI", "3000",
"rv64i/WALLY-SRAI", "3000",
"rv64i/WALLY-JAL", "4000",
"rv64i/WALLY-JALR", "3000",
"rv64i/WALLY-STORE", "3000",
"rv64i/WALLY-ADDIW", "3000",
"rv64i/WALLY-SLLIW", "3000",
"rv64i/WALLY-SRLIW", "3000",
"rv64i/WALLY-SRAIW", "3000",
"rv64i/WALLY-ADDW", "4000",
"rv64i/WALLY-SUBW", "4000",
"rv64i/WALLY-SLLW", "3000",
"rv64i/WALLY-SRLW", "3000",
"rv64i/WALLY-SRAW", "3000",
"rv64i/WALLY-BEQ" ,"5000",
"rv64i/WALLY-BNE", "5000 ",
"rv64i/WALLY-BLTU", "5000 ",
"rv64i/WALLY-BLT", "5000",
"rv64i/WALLY-BGE", "5000 ",
"rv64i/WALLY-BGEU", "5000 ",
"rv64i/WALLY-CSRRW", "4000",
"rv64i/WALLY-CSRRS", "4000",
"rv64i/WALLY-CSRRC", "5000",
"rv64i/WALLY-CSRRWI", "4000",
"rv64i/WALLY-CSRRSI", "4000",
"rv64i/WALLY-CSRRCI", "4000" */
};
string tests32a[] = '{
@ -585,11 +491,11 @@ string tests32f[] = '{
tests = tests64p;
else begin
tests = {tests64i};
/* tests = {tests64p,tests64i, tests64periph};
// tests = {tests64p,tests64i, tests64periph};
if (`C_SUPPORTED) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc};
// else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m};
if (`F_SUPPORTED) tests = {tests64f, tests};
/* if (`F_SUPPORTED) tests = {tests64f, tests};
if (`D_SUPPORTED) tests = {tests64d, tests};
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
if (`A_SUPPORTED) tests = {tests64a, tests}; */
@ -629,7 +535,7 @@ string tests32f[] = '{
// Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.icache.controller.FinalInstrRawF,
dut.hart.ifu.icache.FinalInstrRawF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
@ -661,9 +567,9 @@ string tests32f[] = '{
bootroot = "../../imperas-riscv-tests/";
tvroot = "/home/harris/github/riscv-arch-test/";
memfilename = {tvroot, "work/", tests[test], ".elf.memfile"};
romfilename = {bootroot, "imperas-boottim.txt"};
// romfilename = {bootroot, "imperas-boottim.txt"};
$readmemh(memfilename, dut.uncore.dtim.RAM);
$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
// $readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
ProgramAddrMapFile = {tvroot, "work/", tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {tvroot, "work/", tests[test], ".elf.objdump.lab"};
$display("Read memfile %s", memfilename);

2
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -755,7 +755,7 @@ module riscvassertions();
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented");
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");