Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -58,15 +58,15 @@
 // Cache configuration.  Sizes should be a power of two
 // typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
 `define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 2048
+`define DCACHE_WAYSIZEINBYTES 4096
 `define DCACHE_BLOCKLENINBITS 256
 `define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 1
+`define ICACHE_NUMWAYS 4
 `define ICACHE_WAYSIZEINBYTES 4096
 `define ICACHE_BLOCKLENINBITS 256
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
+`define PMP_ENTRIES 64
 
 // Address space
 `define RESET_VECTOR 64'h80000000

wally-pipelined/src/fpu/fsm.sv

@@ -90,7 +90,22 @@ module fsm (
 		    sel_muxb = 3'b000;		    
 		    sel_muxr = 1'b0;
 		    NEXT_STATE = S13;
-		 end 	       
+		 end 	   
+	       else
+		 begin
+		    done = 1'b0;
+		    divBusy = 1'b0;
+		    load_rega = 1'b0;
+		    load_regb = 1'b0;
+		    load_regc = 1'b0;
+		    load_regd = 1'b0;		    
+		    load_regr = 1'b0;
+		    load_regs = 1'b0;		    		    
+		    sel_muxa = 3'b000;
+		    sel_muxb = 3'b000;		    
+		    sel_muxr = 1'b0;
+		    NEXT_STATE = S0;
+		 end
 	    end // case: S0
 	  S1:
 	    begin