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https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
fix regression
This commit is contained in:
parent
f94a13e242
commit
b1be8f4858
@ -31,7 +31,7 @@ configs = [
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TestCase(
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name="buildroot",
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cmd="vsim -do wally-buildroot-batch.do -c > {}",
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grepstr="loaded 6000 instructions"
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grepstr="8900000 instructions"
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),
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TestCase(
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name="arch64",
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@ -81,7 +81,7 @@ def main():
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"""Run the tests and count the failures"""
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# Scale the number of concurrent processes to the number of test cases, but
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# max out at 12 concurrent processes to not overwhelm the system
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TIMEOUT_DUR = 600 # seconds
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TIMEOUT_DUR = 1800 # seconds
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try:
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os.mkdir("regression_logs")
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except:
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@ -363,38 +363,40 @@ module testbench();
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InstrCountW += 1;
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// turn on waves at certain point
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if (InstrCountW == waveOnICount) $stop;
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// print progress message
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if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
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// check PCW
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fault = 0;
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if(PCW != ExpectedPCW) begin
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$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
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fault = 1;
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$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
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fault = 1;
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end
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// check instruction value
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if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
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$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
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fault = 1;
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$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
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fault = 1;
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end
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// check the number of instructions
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if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
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$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
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if(!`DontHaltOnCSRMisMatch) fault = 1;
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$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
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if(!`DontHaltOnCSRMisMatch) fault = 1;
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end
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#2; // delay 2 ns.
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if(`DEBUG_TRACE > 2) begin
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$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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end
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if (RegWriteW == "GPR") begin
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if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
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$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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fault = 1;
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end
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if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
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$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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fault = 1;
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end
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if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
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$display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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