mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
This commit is contained in:
James E. Stine
parent
129ef03b2d
commit
49721a169b
@ -50,6 +50,7 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
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supply0 vss;
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logic [59:0] muxa_out, muxb_out;
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logic muxr_out;
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logic [10:0] ia_div, ia_sqrt;
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logic [59:0] ia_out;
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logic [119:0] mul_out;
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@ -67,8 +68,8 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
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// Check if exponent is odd for sqrt
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// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
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assign d2 = (exp_odd&op_type) ? {vss,d,6'h0} : {d,7'h0};
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assign n2 = op_type ? d2 : {n,7'h0};
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assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0};
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assign n2 = op_type ? d2 : {n, 7'h0};
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// IA div/sqrt
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sbtm_div ia1 (d[52:41], ia_div);
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@ -137,7 +138,7 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
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flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe);
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// CPA (from CSA)/Remainder addition/subtraction
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assign {cout1, mul_out} = Sum_pipe + Carry_pipe + muxr_pipe;
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assign mul_out = Sum_pipe + Carry_pipe + {119'h0, muxr_pipe};
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// One's complement instead of two's complement (for hw efficiency)
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assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]};
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mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out);
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@ -154,13 +155,13 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
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flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2);
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// Assuming [1,2) - q1
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assign {cout2, q_out1} = regb_out + q_const;
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assign {cout3, qp_out1} = regb_out + qp_const;
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assign {cout4, qm_out1} = regb_out + qm_const + 1'b1;
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assign q_out1 = regb_out + q_const;
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assign qp_out1 = regb_out + qp_const;
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assign qm_out1 = regb_out + qm_const + 1'b1;
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// Assuming [0.5,1) - q0
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assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const;
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assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const;
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assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1;
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assign q_out0 = {regb_out[58:0], 1'b0} + q_const;
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assign qp_out0 = {regb_out[58:0], 1'b0} + qp_const;
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assign qm_out0 = {regb_out[58:0], 1'b0} + qm_const + 1'b1;
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// Stage 3
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// Assuming [1,2)
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@ -78,13 +78,18 @@ module fpdiv_pipe (
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logic [2:0] sel_muxa, sel_muxb;
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logic sel_muxr;
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logic load_rega, load_regb, load_regc, load_regd, load_regr;
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logic load_regp;
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logic donev, sel_muxrv, sel_muxsv;
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logic [1:0] sel_muxav, sel_muxbv;
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logic load_regav, load_regbv, load_regcv;
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logic load_regrv, load_regsv;
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logic load_regp, load_regs;
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logic exp_odd, exp_odd1;
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logic start1;
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logic P1;
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logic op_type1;
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logic [12:0] expF1;
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logic [52:0] mantissaA1;
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logic [52:0] mantissaB1;
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logic [2:0] sel_inv1;
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logic signResult1;
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logic Invalid1;
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// op_type : fdiv=0, fsqrt=1
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assign Float1 = op1;
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@ -94,11 +99,9 @@ module fpdiv_pipe (
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exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid);
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// Determine Sign/Mantissa
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assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type;
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assign signResult = ((Float1[63]^Float2[63])&~op_type);
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assign mantissaA = {vdd, Float1[51:0]};
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assign mantissaB = {vdd, Float2[51:0]};
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// Early-ending detection
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assign early_detection = |mantissaB[31:0];
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// Perform Exponent Subtraction - expA - expB + Bias
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assign exp1 = {2'b0, Float1[62:52]};
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@ -106,26 +109,14 @@ module fpdiv_pipe (
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// bias : DP = 2^{11-1}-1 = 1023
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assign bias = {3'h0, 10'h3FF};
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// Divide exponent
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assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias};
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assign exp_diff = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias};
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// Sqrt exponent (check if exponent is odd)
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assign exp_odd = Float1[52] ? vss : vdd;
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assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd};
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assign exp_odd = Float1[52] ? 1'b0 : 1'b1;
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assign exp_sqrt = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd};
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// Choose correct exponent
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assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
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logic exp_odd1;
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logic P1;
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logic op_type1;
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logic [12:0] expF1;
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logic [52:0] mantissaA1;
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logic [52:0] mantissaB1;
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logic [2:0] sel_inv1;
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logic DenormIn1;
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logic signResult1;
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logic Invalid1;
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flopenr #(1) rega (clk, reset, 1'b1, exp_odd, exp_odd1);
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flopenr #(1) regb (clk, reset, 1'b1, P, P1);
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flopenr #(1) regc (clk, reset, 1'b1, op_type, op_type1);
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@ -134,33 +125,32 @@ module fpdiv_pipe (
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flopenr #(53) regf (clk, reset, 1'b1, mantissaB, mantissaB1);
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flopenr #(1) regg (clk, reset, 1'b1, start, start1);
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flopenr #(3) regh (clk, reset, 1'b1, sel_inv, sel_inv1);
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flopenr #(1) regi (clk, reset, 1'b1, DenormIn, DenormIn1);
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flopenr #(1) regj (clk, reset, 1'b1, signResult, signResult1);
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flopenr #(1) regk (clk, reset, 1'b1, Invalid, Invalid1);
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// Main Goldschmidt/Division Routine
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divconv_pipe goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out,
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regr_out, mantissaB1, mantissaA1,
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sel_muxa, sel_muxb, sel_muxr, reset, clk,
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load_rega, load_regb, load_regc, load_regd,
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load_regr, load_regs, load_regp,
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P1, op_type1, exp_odd1);
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divconv_pipe goldy (.q1, .qm1, .qp1, .q0, .qm0, .qp0,
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.rega_out, .regb_out, .regc_out, .regd_out,
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.regr_out, .d(mantissaB1), .n(mantissaA1),
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.sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk,
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.load_rega, .load_regb, .load_regc, .load_regd,
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.load_regr, .load_regs, .load_regp,
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.P(P1), .op_type(op_type1), .exp_odd(exp_odd1));
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// FSM : control divider
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fsm_fpdiv_pipe control (.clk, .reset, .start, .op_type, .P,
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fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P1),
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.done, .load_rega, .load_regb, .load_regc, .load_regd,
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.load_regr, .load_regs, .load_regp,
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.sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE));
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// Round the mantissa to a 52-bit value, with the leading one
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// removed. The rounding units also handles special cases and
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// set the exception flags.
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rounder_div round1 (.rm, .P, .OvEn, .UnEn, .exp_diff(expF),
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.sel_inv, .Invalid, .SignR(signResult),
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rounder_div round1 (.rm, .P(P1), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1),
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.sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1),
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.Float1(op1), .Float2(op2),
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.XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ,
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.XInfQ, .YInfQ, .op_type,
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.XInfQ, .YInfQ, .op_type(op_type1),
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.q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out,
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.Result, .Flags(FlagsIn));
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@ -66,67 +66,69 @@ module fpu (
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logic FDivStartD, FDivStartE; // Start division or squareroot
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logic FWriteIntD; // Write to integer register
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logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
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logic [1:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select the result written to FP register
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logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
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logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
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logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM; // Select the result written to the integer resister
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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logic [1:0] FResultSelD, FResultSelE; // Select the result written to FP register
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logic [1:0] FResultSelM, FResultSelW; // Select the result written to FP register
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logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
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logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
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logic [1:0] FIntResSelD, FIntResSelE; // Select the result written to the integer resister
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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// regfile signals
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [63:0] FSrcXE, FSrcXM; // Input 1 to the various units (after forwarding)
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logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
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logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [63:0] FSrcXE; // Input 1 to the various units (after forwarding)
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logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
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logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
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// unpacking signals
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logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
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logic XSgnM, YSgnM; // input's sign - memory stage
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logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
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logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
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logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
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logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
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logic [10:0] BiasE; // bias based on precision (single=7f double=3ff - max expoent/2)
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XNaNQ, YNaNQ; // is the input a NaN - divide
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
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logic XZeroQ, YZeroQ; // is the input zero - divide
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XInfQ, YInfQ; // is the input infinity - divide
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logic XExpMaxE; // is the exponent all ones (max value)
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logic XNormE; // is normal
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logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
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logic XSgnM, YSgnM; // input's sign - memory stage
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logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
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logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
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logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
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logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
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logic [10:0] BiasE; // bias based on precision (single=7f double=3ff)
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XNaNQ, YNaNQ; // is the input a NaN - divide
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
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logic XZeroQ, YZeroQ; // is the input zero - divide
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XInfQ, YInfQ; // is the input infinity - divide
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logic XExpMaxE; // is the exponent all ones (max value)
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logic XNormE; // is normal
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logic FmtQ;
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logic FDivStartQ;
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// result and flag signals
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logic [63:0] FDivResM, FDivResW; // divide/squareroot result
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logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
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logic [63:0] FMAResM, FMAResW; // FMA/multiply result
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logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
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logic [63:0] ReadResW; // read result (load instruction)
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logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
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logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
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logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
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logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
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logic [63:0] ClassResE, ClassResM; // classify result
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logic [63:0] CmpResE, CmpResM; // compare result
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logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
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logic [63:0] SgnResE, SgnResM; // sign injection result
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logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
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logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
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logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
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logic [63:0] FDivResM, FDivResW; // divide/squareroot result
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logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
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logic [63:0] FMAResM, FMAResW; // FMA/multiply result
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logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
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logic [63:0] ReadResW; // read result (load instruction)
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logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
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logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
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logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
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logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
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logic [63:0] ClassResE, ClassResM; // classify result
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logic [63:0] CmpResE, CmpResM; // compare result
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logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
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logic [63:0] SgnResE, SgnResM; // sign injection result
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logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
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logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
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logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
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logic [`XLEN-1:0] FIntResE;
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logic [63:0] FPUResultW; // final FP result being written to the FP register
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logic [63:0] FPUResultW; // final FP result being written to the FP register
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// other signals
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logic FDivSqrtDoneE; // is divide done
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logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
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logic FDivClk; // clock for divide/squareroot unit
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logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
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logic FDivSqrtDoneE; // is divide done
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logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
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logic FDivClk; // clock for divide/squareroot unit
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logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
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// DECODE STAGE
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@ -198,14 +200,14 @@ module fpu (
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floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
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.clear(FDivSqrtDoneE),
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.reset(reset), .clk(FDivBusyE));
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floprc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}),
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.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}),
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floprc #(7) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE}),
|
||||
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ}),
|
||||
.clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
|
||||
.reset, .clk(clk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1),
|
||||
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ,
|
||||
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
|
||||
.reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
|
||||
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ,
|
||||
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
|
||||
|
||||
// convert from signle to double and vice versa
|
||||
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
|
||||
|
||||
@ -42,7 +42,7 @@ module fsm_fpdiv_pipe (
|
||||
output logic divBusy
|
||||
);
|
||||
|
||||
// div64 : S0-S14 (15 cycles)
|
||||
// div64 : S1-S14 (14 cycles)
|
||||
// sqrt64 : S15-S35 (21 cycles)
|
||||
// div32: S36-S47 (12 cycles)
|
||||
// sqrt32 : S48-S64 (17 cycles)
|
||||
@ -52,7 +52,7 @@ module fsm_fpdiv_pipe (
|
||||
S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
|
||||
S40, S41, S42, S43, S44, S45, S46, S47, S48, S49,
|
||||
S50, S51, S52, S53, S54, S55, S56, S57, S58, S59,
|
||||
S60, S61, S62, S63, S64} statetype;
|
||||
S60, S61, S62, S63, S64, S65} statetype;
|
||||
|
||||
statetype current_state, next_state;
|
||||
|
||||
@ -72,7 +72,7 @@ module fsm_fpdiv_pipe (
|
||||
if (start==1'b0)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b0;
|
||||
divBusy = 1'b0;
|
||||
load_rega = 1'b0;
|
||||
load_regb = 1'b0;
|
||||
load_regc = 1'b0;
|
||||
@ -83,9 +83,28 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end // if (start==1'b0)
|
||||
else
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
load_rega = 1'b0;
|
||||
load_regb = 1'b0;
|
||||
load_regc = 1'b0;
|
||||
load_regd = 1'b0;
|
||||
load_regr = 1'b0;
|
||||
load_regs = 1'b0;
|
||||
load_regp = 1'b0;
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state = S65;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b0 && P==1'b0)
|
||||
end
|
||||
S65:
|
||||
begin
|
||||
if (op_type==1'b0 && P==1'b0)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
@ -99,9 +118,9 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S1;
|
||||
next_state = S1;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b0 && P==1'b1)
|
||||
else if (op_type==1'b0 && P==1'b1)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
@ -115,9 +134,9 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S36;
|
||||
next_state = S36;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b1 && P==1'b0)
|
||||
else if (op_type==1'b1 && P==1'b0)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
@ -131,9 +150,9 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S15;
|
||||
next_state = S15;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b1 && P==1'b1)
|
||||
else if (op_type==1'b1 && P==1'b1)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
@ -147,7 +166,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S48;
|
||||
next_state = S48;
|
||||
end
|
||||
else
|
||||
begin
|
||||
@ -163,7 +182,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
end // case: S0
|
||||
// div64
|
||||
@ -181,7 +200,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S2;
|
||||
next_state = S2;
|
||||
end // case: S1
|
||||
S2: // iteration 1
|
||||
begin
|
||||
@ -197,7 +216,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S3;
|
||||
next_state = S3;
|
||||
end
|
||||
S3:
|
||||
begin
|
||||
@ -213,7 +232,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S4;
|
||||
next_state = S4;
|
||||
end
|
||||
S4: // iteration 2
|
||||
begin
|
||||
@ -229,7 +248,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S5;
|
||||
next_state = S5;
|
||||
end
|
||||
S5:
|
||||
begin
|
||||
@ -245,7 +264,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0; // add
|
||||
next_state <= S6;
|
||||
next_state = S6;
|
||||
end
|
||||
S6: // iteration 3
|
||||
begin
|
||||
@ -261,7 +280,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S7;
|
||||
next_state = S7;
|
||||
end
|
||||
S7:
|
||||
begin
|
||||
@ -277,7 +296,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S8;
|
||||
next_state = S8;
|
||||
end // case: S7
|
||||
S8:
|
||||
begin
|
||||
@ -293,7 +312,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S9;
|
||||
next_state = S9;
|
||||
end // case: S7
|
||||
S9: // q,qm,qp
|
||||
begin
|
||||
@ -309,7 +328,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S10;
|
||||
next_state = S10;
|
||||
end // case: S9
|
||||
S10: // rem
|
||||
begin
|
||||
@ -325,7 +344,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S11;
|
||||
next_state = S11;
|
||||
end
|
||||
S11:
|
||||
begin
|
||||
@ -341,7 +360,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S12;
|
||||
next_state = S12;
|
||||
end // case: S11
|
||||
S12:
|
||||
begin
|
||||
@ -357,7 +376,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S13;
|
||||
next_state = S13;
|
||||
end
|
||||
S13:
|
||||
begin
|
||||
@ -373,7 +392,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S14;
|
||||
next_state = S14;
|
||||
end
|
||||
S14:
|
||||
begin
|
||||
@ -389,7 +408,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
// sqrt64
|
||||
S15:
|
||||
@ -406,7 +425,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S16;
|
||||
next_state = S16;
|
||||
end
|
||||
S16:
|
||||
begin
|
||||
@ -422,7 +441,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b100;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S17;
|
||||
next_state = S17;
|
||||
end
|
||||
S17:
|
||||
begin
|
||||
@ -438,7 +457,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S18;
|
||||
next_state = S18;
|
||||
end
|
||||
S18: // iteration 1
|
||||
begin
|
||||
@ -454,7 +473,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S19;
|
||||
next_state = S19;
|
||||
end
|
||||
S19: // iteration 1
|
||||
begin
|
||||
@ -470,7 +489,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S20;
|
||||
next_state = S20;
|
||||
end
|
||||
S20:
|
||||
begin
|
||||
@ -486,7 +505,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S21;
|
||||
next_state = S21;
|
||||
end
|
||||
S21:
|
||||
begin
|
||||
@ -502,7 +521,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S22;
|
||||
next_state = S22;
|
||||
end
|
||||
S22: // iteration 2
|
||||
begin
|
||||
@ -518,7 +537,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S23;
|
||||
next_state = S23;
|
||||
end // case: S18
|
||||
S23:
|
||||
begin
|
||||
@ -534,7 +553,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S24;
|
||||
next_state = S24;
|
||||
end
|
||||
S24:
|
||||
begin
|
||||
@ -550,7 +569,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S25;
|
||||
next_state = S25;
|
||||
end
|
||||
S25:
|
||||
begin
|
||||
@ -566,7 +585,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S26;
|
||||
next_state = S26;
|
||||
end
|
||||
S26: // iteration 3
|
||||
begin
|
||||
@ -582,7 +601,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S27;
|
||||
next_state = S27;
|
||||
end // case: S21
|
||||
S27:
|
||||
begin
|
||||
@ -598,7 +617,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S28;
|
||||
next_state = S28;
|
||||
end
|
||||
S28:
|
||||
begin
|
||||
@ -614,7 +633,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S29;
|
||||
next_state = S29;
|
||||
end
|
||||
S29:
|
||||
begin
|
||||
@ -630,7 +649,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S30;
|
||||
next_state = S30;
|
||||
end // case: S23
|
||||
S30: // q,qm,qp
|
||||
begin
|
||||
@ -646,7 +665,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S31;
|
||||
next_state = S31;
|
||||
end
|
||||
S31: // rem
|
||||
begin
|
||||
@ -662,7 +681,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S32;
|
||||
next_state = S32;
|
||||
end // case: S25
|
||||
S32:
|
||||
begin
|
||||
@ -678,8 +697,8 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S33;
|
||||
end // case: S34
|
||||
next_state = S33;
|
||||
end
|
||||
S33:
|
||||
begin
|
||||
done = 1'b0;
|
||||
@ -694,7 +713,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S34;
|
||||
next_state = S34;
|
||||
end
|
||||
S34: // done
|
||||
begin
|
||||
@ -710,9 +729,9 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S35;
|
||||
end // case: S34
|
||||
S34:
|
||||
next_state = S35;
|
||||
end
|
||||
S35:
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b0;
|
||||
@ -726,7 +745,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
// div32
|
||||
S36:
|
||||
@ -743,7 +762,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S37;
|
||||
next_state = S37;
|
||||
end // case: S1
|
||||
S37: // iteration 1
|
||||
begin
|
||||
@ -759,7 +778,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S38;
|
||||
next_state = S38;
|
||||
end
|
||||
S38:
|
||||
begin
|
||||
@ -775,7 +794,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S39;
|
||||
next_state = S39;
|
||||
end
|
||||
S39: // iteration 2
|
||||
begin
|
||||
@ -791,7 +810,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S40;
|
||||
next_state = S40;
|
||||
end
|
||||
S40:
|
||||
begin
|
||||
@ -807,7 +826,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S41;
|
||||
next_state = S41;
|
||||
end
|
||||
S41:
|
||||
begin
|
||||
@ -823,7 +842,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S42;
|
||||
next_state = S42;
|
||||
end
|
||||
S42: // q,qm,qp
|
||||
begin
|
||||
@ -839,7 +858,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S43;
|
||||
next_state = S43;
|
||||
end // case: S9
|
||||
S43: // rem
|
||||
begin
|
||||
@ -855,7 +874,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S44;
|
||||
next_state = S44;
|
||||
end
|
||||
S44:
|
||||
begin
|
||||
@ -871,7 +890,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S45;
|
||||
next_state = S45;
|
||||
end // case: S11
|
||||
S45:
|
||||
begin
|
||||
@ -887,7 +906,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S46;
|
||||
next_state = S46;
|
||||
end
|
||||
S46: // done
|
||||
begin
|
||||
@ -903,7 +922,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S47;
|
||||
next_state = S47;
|
||||
end
|
||||
S47:
|
||||
begin
|
||||
@ -919,7 +938,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
// sqrt32
|
||||
S48:
|
||||
@ -936,7 +955,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S49;
|
||||
next_state = S49;
|
||||
end
|
||||
S49:
|
||||
begin
|
||||
@ -952,7 +971,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b100;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S50;
|
||||
next_state = S50;
|
||||
end
|
||||
S50:
|
||||
begin
|
||||
@ -968,7 +987,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S51;
|
||||
next_state = S51;
|
||||
end
|
||||
S51: // iteration 1
|
||||
begin
|
||||
@ -984,7 +1003,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S52;
|
||||
next_state = S52;
|
||||
end
|
||||
S52: // iteration 1
|
||||
begin
|
||||
@ -1000,7 +1019,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S53;
|
||||
next_state = S53;
|
||||
end
|
||||
S53:
|
||||
begin
|
||||
@ -1016,7 +1035,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S54;
|
||||
next_state = S54;
|
||||
end
|
||||
S54:
|
||||
begin
|
||||
@ -1032,7 +1051,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S55;
|
||||
next_state = S55;
|
||||
end
|
||||
S55: // iteration 2
|
||||
begin
|
||||
@ -1048,7 +1067,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S56;
|
||||
next_state = S56;
|
||||
end // case: S18
|
||||
S56:
|
||||
begin
|
||||
@ -1064,7 +1083,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S57;
|
||||
next_state = S57;
|
||||
end
|
||||
S57:
|
||||
begin
|
||||
@ -1080,7 +1099,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S58;
|
||||
next_state = S58;
|
||||
end
|
||||
S58:
|
||||
begin
|
||||
@ -1096,7 +1115,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S59;
|
||||
next_state = S59;
|
||||
end
|
||||
S59: // q,qm,qp
|
||||
begin
|
||||
@ -1112,7 +1131,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S60;
|
||||
next_state = S60;
|
||||
end
|
||||
S60: // rem
|
||||
begin
|
||||
@ -1128,7 +1147,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S61;
|
||||
next_state = S61;
|
||||
end // case: S25
|
||||
S61:
|
||||
begin
|
||||
@ -1144,7 +1163,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
next_state <= S62;
|
||||
next_state = S62;
|
||||
end // case: S34
|
||||
S62:
|
||||
begin
|
||||
@ -1160,7 +1179,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S63;
|
||||
next_state = S63;
|
||||
end
|
||||
S63: // done
|
||||
begin
|
||||
@ -1176,7 +1195,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S64;
|
||||
next_state = S64;
|
||||
end // case: S34
|
||||
S64:
|
||||
begin
|
||||
@ -1192,7 +1211,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
@ -1208,7 +1227,7 @@ module fsm_fpdiv_pipe (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
next_state <= S0;
|
||||
next_state = S0;
|
||||
end
|
||||
endcase // case(current_state)
|
||||
end // always @ (current_state or X)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user