Divider mostly cleaned up

wally-pipelined/src/muldiv/intdivrestoring.sv

@@ -50,10 +50,10 @@ module intdivrestoring (
   // Saving the inputs is the most hardware-efficient way to fix the issue.
   flopen #(`XLEN) dsavereg(~clk, StartDivideE, DE, DSavedE); 
   flopen #(`XLEN) xsavereg(~clk, StartDivideE, XE, XSavedE);
-	flopenrc #(1) SignedDivideMReg(clk, reset, FlushM, ~StallM, SignedDivideE, SignedDivideM);
+  flopenrc #(1) SignedDivideMReg(clk, reset, FlushM, ~StallM, SignedDivideE, SignedDivideM);
   assign SignD = DSavedE[`XLEN-1]; // *** do some of these need pipelining for consecutive divides?
   assign SignX = XSavedE[`XLEN-1];
-  assign div0 = (DSavedE == 0); // *** eventually replace with just the negedge saved D
+  assign div0 = (DSavedE == 0);
 
   // Take absolute value for signed operations
   neg #(`XLEN) negd(DSavedE, DnE);
@@ -72,7 +72,7 @@ module intdivrestoring (
   intdivrestoringstep step1(Win, XQin, DAbsB, W1, XQ1);
   intdivrestoringstep step2(W1, XQ1, DAbsB, Wnext, XQnext);
 
-  flopen #(`XLEN) wreg(clk, BusyE, Wnext, W); // *** could become just busy once start moves to its own cycle
+  flopen #(`XLEN) wreg(clk, BusyE, Wnext, W); 
   flopen #(`XLEN) xreg(clk, BusyE, XQnext, XQ);
 
   // Output selection logic in Memory Stage
@@ -105,24 +105,8 @@ module intdivrestoring (
     end else if (done) begin
         done = 0;
         BusyE = 0;
-    end
-    //assign init = (step == 0);
- 
+    end 
 
-endmodule // muldiv
-
-
-module intdivrestoringstep(
-  input  logic [`XLEN-1:0] W, XQ, DAbsB,
-  output logic [`XLEN-1:0] WOut, XQOut);
-
-  logic [`XLEN-1:0] WShift, WPrime;
-  logic qi, qib;
-  
-  assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
-  assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
-  assign qi = ~qib;
-  mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
-endmodule
+endmodule 
 
 // *** clean up internal signals

wally-pipelined/src/muldiv/intdivrestoringstep.sv

@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// intdivrestoringstep.sv
+//
+// Written: David_Harris@hmc.edu 2 October 2021
+// Modified: 
+//
+// Purpose: Restoring integer division using a shift register and subtractor
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module intdivrestoringstep(
+  input  logic [`XLEN-1:0] W, XQ, DAbsB,
+  output logic [`XLEN-1:0] WOut, XQOut);
+
+  logic [`XLEN-1:0] WShift, WPrime;
+  logic qi, qib;
+  
+  assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
+  assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
+  assign qi = ~qib;
+  mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
+endmodule
+