mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
Partially sd card read on fpga.
This commit is contained in:
Ross Thompson
parent
99070127d8
commit
db18aac9af
@ -40,7 +40,7 @@ vsim workopt -fsmdebug
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#profile on
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do wave.do
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do fpga-wave.do
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add log -r /*
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-- Run the Simulation
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File diff suppressed because it is too large
Load Diff
@ -337,7 +337,7 @@ module SDC
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.o_ERROR_CODE_Q(ErrorCode),
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.o_FATAL_ERROR(FatalError),
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.i_COUNT_IN_MAX(-8'd62),
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.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
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.LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
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endmodule
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@ -28,81 +28,81 @@
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module sd_cmd_fsm
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(
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input logic CLK, // HS
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input logic CLK, // HS
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//i_SLOWER_CLK : in std_logic;
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input logic i_RST, // reset FSM,
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input logic i_RST, // reset FSM,
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// MUST COME OUT OF RESET
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// SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
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output logic [18:0] o_TIMER_IN,
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input logic [18:0] i_TIMER_OUT,
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output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
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output logic [7:0] o_COUNTER_IN,
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input logic [7:0] i_COUNTER_OUT,
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output logic o_SD_CLK_EN, // Clock Gaters
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input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
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output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
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output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
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input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
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input logic [1:0] i_USES_DAT,
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input logic [6:0] i_OPCODE,
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input logic [2:0] i_R_TYPE,
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(* mark_debug = "true" *) output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
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(* mark_debug = "true" *) output logic [18:0] o_TIMER_IN,
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(* mark_debug = "true" *) input logic [18:0] i_TIMER_OUT,
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(* mark_debug = "true" *) output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
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(* mark_debug = "true" *) output logic [7:0] o_COUNTER_IN,
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(* mark_debug = "true" *) input logic [7:0] i_COUNTER_OUT,
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(* mark_debug = "true" *) output logic o_SD_CLK_EN, // Clock Gaters
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(* mark_debug = "true" *) input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
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(* mark_debug = "true" *) output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
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(* mark_debug = "true" *) output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
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(* mark_debug = "true" *) input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
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(* mark_debug = "true" *) input logic [1:0] i_USES_DAT,
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(* mark_debug = "true" *) input logic [6:0] i_OPCODE,
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(* mark_debug = "true" *) input logic [2:0] i_R_TYPE,
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// bit masks
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input logic [31:0] i_NO_REDO_MASK,
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input logic [31:0] i_NO_REDO_ANS,
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input logic [31:0] i_NO_ERROR_MASK,
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input logic [31:0] i_NO_ERROR_ANS,
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output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
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(* mark_debug = "true" *) input logic [31:0] i_NO_REDO_MASK,
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(* mark_debug = "true" *) input logic [31:0] i_NO_REDO_ANS,
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(* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_MASK,
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(* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_ANS,
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(* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
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// TX Components
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output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
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output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
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output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
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output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
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(* mark_debug = "true" *) output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
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(* mark_debug = "true" *) output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
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(* mark_debug = "true" *) output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
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(* mark_debug = "true" *) output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
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// TX Memory
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output logic o_CMD_TX_IS_CMD55_RST,
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output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
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(* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_RST,
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(* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
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// 55, so the subsequent command is to be
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// viewed as ACMD by the SD card.
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// RX Components
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input logic i_SD_CMD_RX, // serial response input on SD_CMD
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output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
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(* mark_debug = "true" *) input logic i_SD_CMD_RX, // serial response input on SD_CMD
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(* mark_debug = "true" *) output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
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input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
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input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
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output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
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input logic [6:0] i_RX_CRC7,
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(* mark_debug = "true" *) input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
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(* mark_debug = "true" *) input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
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(* mark_debug = "true" *) output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
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(* mark_debug = "true" *) input logic [6:0] i_RX_CRC7,
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// RX Memory
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output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
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(* mark_debug = "true" *) output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
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// Communication to sd_dat_fsm
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output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
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input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
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input logic i_ERROR_CRC16, // repeat last command
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input logic i_ERROR_DAT_TIMES_OUT,
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(* mark_debug = "true" *) output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
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(* mark_debug = "true" *) input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
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(* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
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(* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
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// Commnuication to core
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output logic o_READY_FOR_READ, // tell core that I have completed initialization
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output logic o_SD_RESTARTING, // inform core the need to restart
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input logic i_READ_REQUEST, // core tells me to execute CMD17
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(* mark_debug = "true" *) output logic o_READY_FOR_READ, // tell core that I have completed initialization
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(* mark_debug = "true" *) output logic o_SD_RESTARTING, // inform core the need to restart
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(* mark_debug = "true" *) input logic i_READ_REQUEST, // core tells me to execute CMD17
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// Communication to Host
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output logic o_DAT_ERROR_FD_RST,
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output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
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output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
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input logic LIMIT_SD_TIMERS
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(* mark_debug = "true" *) output logic o_DAT_ERROR_FD_RST,
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(* mark_debug = "true" *) output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
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(* mark_debug = "true" *) output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
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(* mark_debug = "true" *) input logic LIMIT_SD_TIMERS
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);
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(* mark_debug = "true" *) logic [4:0] w_next_state, r_curr_state;
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logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
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(* mark_debug = "true" *) logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
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logic [31:0] w_redo_result, w_error_result;
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logic w_ACMD41_init_done;
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logic w_fail_cnt_en, w_fail_count_rst;
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logic [10:0] r_fail_count_out;
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(* mark_debug = "true" *) logic [31:0] w_redo_result, w_error_result;
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(* mark_debug = "true" *) logic w_ACMD41_init_done;
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(* mark_debug = "true" *) logic w_fail_cnt_en, w_fail_count_rst;
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(* mark_debug = "true" *) logic [10:0] r_fail_count_out;
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logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
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logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
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logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
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logic [18:0] Timer_In;
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(* mark_debug = "true" *) logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
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(* mark_debug = "true" *) logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
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(* mark_debug = "true" *) logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
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(* mark_debug = "true" *) logic [18:0] Timer_In;
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localparam s_reset_clear_error_reg = 5'b00000;
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@ -31,11 +31,11 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
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input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
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// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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// io_SD_CMD_z : inout std_logic; // SD CMD Bus
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input logic i_SD_CMD, // CMD Response from card
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output logic o_SD_CMD, // CMD Command from host
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output logic o_SD_CMD_OE, // Direction of SD_CMD
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input logic [3:0] i_SD_DAT, // SD DAT Bus
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output logic o_SD_CLK, // SD CLK Bus
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(* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
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(* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
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(* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
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(* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
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(* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
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// For communication with core cpu
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input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
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output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
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@ -222,7 +222,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
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logic [15:0] r_RCA_Q2;
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// Multiplexer Logics
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logic [132:0] w_instruction_control_bits;
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(* mark_debug = "true" *) logic [132:0] w_instruction_control_bits;
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logic [132:130] w_R_TYPE ;
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logic [129:128] w_USES_DAT ;
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logic [127:96] w_NO_REDO_MASK ;
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@ -255,7 +255,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
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// Tri state IO Driver BC18MIMS
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logic w_SD_CMD_TX_Q; // Write Data
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logic w_SD_CMD_RX; // Read Data
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(* mark_debug = "true" *) logic w_SD_CMD_RX; // Read Data
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// CLOCKS
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@ -1,41 +0,0 @@
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///////////////////////////////////////////
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// ila_0.sv
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//
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// Written: Ross Thompson September 26, 2021
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// Modified:
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//
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// Purpose: stub for simulation. does nothing.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ila_0
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(input logic clk,
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input logic [`XLEN-1:0] probe0,
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input logic [`XLEN-1:0] probe1,
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input logic [`XLEN-1:0] probe2,
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input logic [`XLEN-1:0] probe3,
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input logic probe4,
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input logic [1:0] probe5,
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input logic [31:0] probe6
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);
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endmodule; // ila_0
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@ -50,13 +50,15 @@ module wallypipelinedsoc (
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output logic HMASTLOCK,
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output logic HREADY,
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// I/O Interface
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout,
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output tri1 SDCCmd,
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input logic [3:0] SDCDat,
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output logic SDCCLK
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout,
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input logic SDCCmdIn,
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output logic SDCCmdOut,
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output logic SDCCmdOE,
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input logic [3:0] SDCDatIn,
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output logic SDCCLK
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);
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// to instruction memory *** remove later
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@ -77,14 +79,17 @@ module wallypipelinedsoc (
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logic [31:0] InstrF;
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logic HRESP;
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/* -----\/----- EXCLUDED -----\/-----
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic SDCCmdIn;
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logic [3:0] SDCDatIn;
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-----/\----- EXCLUDED -----/\----- */
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// logic [3:0] SDCDatIn;
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assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
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assign SDCCmdIn = SDCCmd;
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assign SDCDatIn = SDCDat; // when write supported this will be a tristate
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// it turn out vivado cannot infer these at this level of the hierarchy.
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//assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
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//assign SDCCmdIn = SDCCmd;
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//assign SDCDatIn = SDCDat; // when write supported this will be a tristate
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// instantiate processor and memories
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wallypipelinedhart hart(.*);
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@ -55,9 +55,11 @@ module wallypipelinedsocwrapper (
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input UARTSin,
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output UARTSout,
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input ddr4_calib_complete,
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input [3:0] SDCDat,
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input [3:0] SDCDatIn,
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output SDCCLK,
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inout SDCCmd
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input SDCCmdIn,
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output SDCCmdOut,
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output SDCCmdOE
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);
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wire [31:0] GPIOPinsEn;
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@ -109,8 +111,10 @@ module wallypipelinedsocwrapper (
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.GPIOPinsEn(GPIOPinsEn),
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.UARTSin(UARTSin),
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.UARTSout(UARTSout),
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.SDCDat(SDCDat),
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.SDCDatIn(SDCDatIn),
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.SDCCLK(SDCCLK),
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.SDCCmd(SDCCmd));
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.SDCCmdIn(SDCCmdIn),
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.SDCCmdOut(SDCCmdOut),
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.SDCCmdOE(SDCCmdOE));
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endmodule
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@ -519,12 +519,12 @@ string tests32f[] = '{
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logic DCacheFlushDone, DCacheFlushStart;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW, dut.wallypipelinedsoc.hart.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW, dut.wallypipelinedsoc.hart.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
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logging logging(clk, reset, dut.wallypipelinedsoc.uncore.HADDR, dut.wallypipelinedsoc.uncore.HTRANS);
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// pick tests based on modes supported
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initial begin
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@ -568,8 +568,11 @@ string tests32f[] = '{
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string signame, memfilename, romfilename, sdcfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic [3:0] GPIOPinsIn_IO;
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logic [4:0] GPIOPinsOut_IO;
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logic UARTSin, UARTSout;
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logic ddr4_calib_complete;
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logic SDCCLK;
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tri1 SDCCmd;
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@ -594,10 +597,10 @@ string tests32f[] = '{
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wallypipelinedsocwrapper dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.hart.ieu.dp.FlushE,
|
||||
dut.wallypipelinedsoc.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.wallypipelinedsoc.hart.ifu.InstrD, dut.wallypipelinedsoc.hart.ifu.InstrE,
|
||||
dut.wallypipelinedsoc.hart.ifu.InstrM, dut.wallypipelinedsoc.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
@ -630,7 +633,7 @@ string tests32f[] = '{
|
||||
romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"};
|
||||
sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};
|
||||
$readmemh(memfilename, dtim.RAM);
|
||||
$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
|
||||
$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM);
|
||||
$readmemh(sdcfilename, sdcard.FLASHmem);
|
||||
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
|
||||
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.lab"};
|
||||
@ -648,11 +651,11 @@ string tests32f[] = '{
|
||||
always @(negedge clk)
|
||||
begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if (DCacheFlushDone) begin
|
||||
//$display("Code ended with ecall with gp = 1");
|
||||
@ -729,18 +732,20 @@ string tests32f[] = '{
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1));
|
||||
assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1));
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
@ -753,8 +758,8 @@ string tests32f[] = '{
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
@ -794,10 +799,10 @@ module DCacheFlushFSM
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
@ -823,10 +828,10 @@ module DCacheFlushFSM
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user