Ross Thompson 225657b8f9 Fixed bug with or_rows. ... If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.		2021-09-11 15:51:11 -05:00
..
bin	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
config	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
fpu-testfloat/FMA/tbgen	FMA cleanup	2021-08-28 10:53:35 -04:00
linux-testgen	changed fix_mem to not use hardcoded file names	2021-09-09 13:22:24 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
src	Fixed bug with or_rows.	2021-09-11 15:51:11 -05:00
testbench	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00