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Lint cleanup

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This commit is contained in:
David Harris 2021-10-23 08:39:21 -07:00
parent 1b1317e6c3
commit ff409d4fe7
3 changed files with 28 additions and 19 deletions
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6
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -46,11 +46,11 @@ module cachereplacementpolicy
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] = '0;
ReplacementBits[index] <= '0;
end else begin
BlockReplacementBits = ReplacementBits[RAdr];
BlockReplacementBits <= ReplacementBits[RAdr];
if (LRUWriteEn) begin
ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacement;
ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
end
end
end

16
wally-pipelined/src/muldiv/intdivrestoring.sv
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@ -115,19 +115,19 @@ module intdivrestoring (
always_ff @(posedge clk)
if (reset) begin
state = IDLE;
state <= IDLE;
end else if (DivStartE) begin
step = 0;
if (Div0E) state = DONE;
else state = BUSY;
step <= 1;
if (Div0E) state <= DONE;
else state <= BUSY;
end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
step = step + 1;
if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
state = DONE;
state <= DONE;
end
step <= step + 1;
end else if (state == DONE) begin
if (StallM) state = DONE;
else state = IDLE;
if (StallM) state <= DONE;
else state <= IDLE;
end
endmodule

25
wally-pipelined/src/muldiv/redundantmul.sv
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@ -4,7 +4,15 @@
// Written: David_Harris@hmc.edu and ssanghai@hm.edu 10/11/2021
// Modified:
//
// Purpose: redundant multiplier
// Purpose: multiplier with output in redundant carry-sum form
// This can be faster than a mutiplier that requires a final adder to obtain the nonredundant answer.
// The module has several implementations controlled by the DESIGN_COMPILER flag.
// When DESIGN_COMPILER = 1, use the Synopsys DesignWare DW02_multp block. This will give highest quality results
// but doesn't work in simulation or when using different tools
// When DESIGN_COMPILER = 2, use the Wally mult_cs block with Radix 2 Booth encoding and a Wallace Tree
// This simulates and synthesizes, but quality of results ae lower than DesignWare
// Otherwise, just use a nonredundant multiplier and set one word to 0. This is best for FPGAs, which have
// block multipliers, and also simulates fastest.
//
// A component of the Wally configurable RISC-V project.
//
@ -29,18 +37,19 @@ module redundantmul #(parameter WIDTH =8)(
input logic [WIDTH-1:0] a,b,
output logic [2*WIDTH-1:0] out0, out1);
logic [2*WIDTH-1+2:0] tmp_out0;
logic [2*WIDTH-1+2:0] tmp_out1;
//
generate
if (`DESIGN_COMPILER == 1)
if (`DESIGN_COMPILER == 1)
begin
DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
assign out0 = tmp_out0[2*WIDTH-1:0];
assign out1 = tmp_out1[2*WIDTH-1:0];
logic [2*WIDTH-1+2:0] tmp_out0; // DW02_
logic [2*WIDTH-1+2:0] tmp_out1;
DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
assign out0 = tmp_out0[2*WIDTH-1:0];
assign out1 = tmp_out1[2*WIDTH-1:0];
end
else if (`DESIGN_COMPILER == 2)
mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
else begin // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs.
assign out0 = a * b;
assign out1 = 0;