Kevin Kim
|
9c95cba865
|
remove sqrt cycle muxing
|
2024-03-03 18:51:10 -08:00 |
|
Kevin Kim
|
0ff59ff157
|
remove redundant mux
|
2024-03-03 13:00:20 -08:00 |
|
Kevin Kim
|
c32173f163
|
changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix
|
2024-03-03 10:30:18 -08:00 |
|
Kevin Kim
|
6c24afaf98
|
changed cycle count to account for integer bit generation for sqrt
|
2024-03-03 10:29:32 -08:00 |
|
Kevin Kim
|
c45d67f8ba
|
fdivsqrt changes
|
2024-03-02 20:29:03 -08:00 |
|
Kevin Kim
|
77ccc7b319
|
removed square root pre-process muxes
|
2024-03-02 15:55:34 -08:00 |
|
Rose Thompson
|
a22de45631
|
Removed unused storedelay from align.
|
2024-03-02 16:20:31 -06:00 |
|
Rose Thompson
|
8136b45ca7
|
Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
This reverts commit cba3209e7f.
|
2024-03-02 11:55:43 -06:00 |
|
Rose Thompson
|
cba3209e7f
|
Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
|
2024-03-02 11:38:33 -06:00 |
|
Rose Thompson
|
4c3d927474
|
Renamed CacheHit to Hit.
|
2024-03-01 11:00:24 -06:00 |
|
Rose Thompson
|
e72880fd89
|
Changed cachefsm state STATE_HIT to STATE_ACCESS.
|
2024-03-01 09:59:54 -06:00 |
|
Rose Thompson
|
85691f0e8b
|
Simplified and clarified names in cacheLRU.
|
2024-02-29 17:18:01 -06:00 |
|
KelvinTr
|
c110d0bb03
|
Optimized Zbkx
|
2024-02-29 14:51:02 -06:00 |
|
KelvinTr
|
9f53c54f57
|
Optimized Zbkx
|
2024-02-29 14:50:15 -06:00 |
|
KelvinTr
|
e40ae126d3
|
Combined ZBC and ZBKC into one unit
|
2024-02-29 14:17:33 -06:00 |
|
KelvinTr
|
88d93b31b5
|
Combined byteop and revop logic
|
2024-02-29 12:51:42 -06:00 |
|
Rose Thompson
|
90ad5e7dab
|
Updated the cache for book clarity.
|
2024-02-28 17:07:32 -06:00 |
|
KelvinTr
|
01c45ab9d7
|
Fixed K extension changes
|
2024-02-28 17:05:08 -06:00 |
|
David Harris
|
90e89ced1d
|
Fixes for synthesis. HPTW change will break x detection
|
2024-02-26 04:20:08 -08:00 |
|
James E. Stine
|
eb1780a66d
|
control for bitmanip
|
2024-02-24 22:38:21 -06:00 |
|
James E. Stine
|
ce975a6336
|
Add ieu main module for k extension
|
2024-02-24 22:37:04 -06:00 |
|
James E. Stine
|
71cefdbbb2
|
main cvw module
|
2024-02-24 22:35:56 -06:00 |
|
James E. Stine
|
cd2a9b8712
|
Add mux7 for K ext
|
2024-02-24 22:26:21 -06:00 |
|
James E. Stine
|
50cbe54d7b
|
Add datapath.sv
|
2024-02-24 22:22:19 -06:00 |
|
James E. Stine
|
e06bafe972
|
Add alu + controller
|
2024-02-24 22:21:39 -06:00 |
|
Rose Thompson
|
ab750e150f
|
Fixed lint errors for alignment.
|
2024-02-23 14:00:19 -06:00 |
|
Rose Thompson
|
a2d5618d88
|
Added sdc to pma allow shift.
|
2024-02-23 13:46:04 -06:00 |
|
Rose Thompson
|
e84b7cc147
|
Cleanup.
|
2024-02-23 13:00:21 -06:00 |
|
Rose Thompson
|
ae36f1e5a5
|
Merge branch 'main' of github.com:ross144/cvw
|
2024-02-23 09:43:03 -06:00 |
|
Rose Thompson
|
caac48b7f2
|
Removed duplicate endianswap.
|
2024-02-23 09:42:39 -06:00 |
|
Rose Thompson
|
a402883115
|
Simplifications of subword code.
|
2024-02-23 09:41:59 -06:00 |
|
Rose Thompson
|
fbc18abaa0
|
Siginficant cleanup of subwordwritemisaligned.
|
2024-02-22 14:17:15 -06:00 |
|
Rose Thompson
|
45c30267a5
|
Cleanup.
|
2024-02-22 14:08:04 -06:00 |
|
Rose Thompson
|
69d31d50e2
|
Updated subword misaligned.
|
2024-02-22 13:29:39 -06:00 |
|
James E. Stine
|
cdd2aa6379
|
tweak of names
|
2024-02-22 12:27:40 -06:00 |
|
James E. Stine
|
c8468e99c0
|
slight tweak of names
|
2024-02-22 12:27:09 -06:00 |
|
James E. Stine
|
550f50debb
|
Modify ALU to handle Zkne/K extension
|
2024-02-22 11:55:00 -06:00 |
|
Rose Thompson
|
7e1ea1e6d9
|
Beginning subword cleanup.
|
2024-02-22 09:37:16 -06:00 |
|
Rose Thompson
|
1ece6f8eae
|
Swapped to the more compact subwordreadmisaligned.sv.
|
2024-02-22 09:34:16 -06:00 |
|
Rose Thompson
|
3714b2bf4a
|
Non-ideal fix. Added new output from pma which indicates if the write shift should occur.
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
|
2024-02-22 09:14:43 -06:00 |
|
James E. Stine
|
7cb170c19b
|
update on aes_instructions
|
2024-02-21 17:12:50 -06:00 |
|
James E. Stine
|
7097b17785
|
update aes_instructions
|
2024-02-21 17:11:34 -06:00 |
|
James E. Stine
|
ac9068d22c
|
update aes_common with style on separate sv
|
2024-02-21 17:05:58 -06:00 |
|
James E. Stine
|
3d65ea7aba
|
separate aes_shiftword per style file
|
2024-02-20 22:57:59 -06:00 |
|
James E. Stine
|
f700b7da5a
|
separate galois function SV per the style file
|
2024-02-20 22:55:34 -06:00 |
|
Rose Thompson
|
6a9c2d8dc4
|
Closer to getting subword write misaligned working.
|
2024-02-20 20:23:42 -06:00 |
|
James E. Stine
|
32be22565a
|
add kmu instruction
|
2024-02-20 20:18:50 -06:00 |
|
James E. Stine
|
38348f9784
|
Add SHA instructions
|
2024-02-20 20:01:12 -06:00 |
|
James E. Stine
|
2cf1d43ec5
|
add aes instructions
|
2024-02-20 19:39:26 -06:00 |
|
James E. Stine
|
93d9bb4bc4
|
minor changes + date change on copyright
|
2024-02-20 19:13:11 -06:00 |
|
James E. Stine
|
488583aed9
|
minor tweak
|
2024-02-20 18:42:34 -06:00 |
|
James E. Stine
|
0cc0cdeae2
|
initial seed of AES engine
|
2024-02-20 18:31:17 -06:00 |
|
David Harris
|
c77afcb7e6
|
Removed floprc with synchronous reset and synchornous clear
|
2024-02-19 22:28:55 -08:00 |
|
Rose Thompson
|
dac8fc16af
|
Partially working optimized subwordwrite for misaligned.
|
2024-02-19 12:26:29 -06:00 |
|
David Harris
|
9ba35991e3
|
Finished FPU coverage
|
2024-02-15 20:01:28 -08:00 |
|
David Harris
|
36259b4e16
|
Removed unused term affecting cvt coverage
|
2024-02-15 17:46:05 -08:00 |
|
David Harris
|
944e33dcd6
|
Fixed spelling of operation in FPU
|
2024-02-15 17:22:32 -08:00 |
|
David Harris
|
c664c9717d
|
Commented fcvtmod behavior in specialcase
|
2024-02-15 17:19:21 -08:00 |
|
Rose Thompson
|
1fd678b433
|
Optimized the align logic for loads.
|
2024-02-14 12:14:19 -06:00 |
|
David Harris
|
6f53adad80
|
ifu cachefsm coverage
|
2024-02-08 13:15:06 -08:00 |
|
Kevin Kim
|
15da037794
|
added back comment
|
2024-02-07 15:40:52 -08:00 |
|
Kevin Kim
|
61c8b4d269
|
shift correction fix
|
2024-02-07 15:04:19 -08:00 |
|
David Harris
|
e7364290e3
|
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
|
2024-02-07 06:27:53 -08:00 |
|
David Harris
|
c41e1c3a1c
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-02-04 19:02:49 -08:00 |
|
David Harris
|
66c1c71a56
|
Coverage improvements
|
2024-02-04 18:56:40 -08:00 |
|
Rose Thompson
|
7a4d485f5b
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-02-04 14:19:50 -06:00 |
|
David Harris
|
5d8d82414b
|
Coverage improvements
|
2024-02-04 11:40:38 -08:00 |
|
harshinisrinath
|
c7b647bde7
|
Wrote exclusions for ifu and lsu peripherals which were always supported
|
2024-02-01 17:12:33 -08:00 |
|
Rose Thompson
|
bd06a5ff88
|
Rough draft removal of duplicate BPBTAWrongE logic.
|
2024-02-01 16:57:33 -06:00 |
|
Rose Thompson
|
e900bb09db
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-02-01 12:12:05 -06:00 |
|
Rose Thompson
|
87d91c5b14
|
Coverage updates.
|
2024-02-01 12:12:01 -06:00 |
|
David Harris
|
1c62c5e433
|
Fixed logic to work with FLEN < XLEN
|
2024-01-31 20:24:16 -08:00 |
|
Rose Thompson
|
ccf61853cf
|
New coverage for ebu.
|
2024-01-31 14:55:25 -06:00 |
|
David Harris
|
0abfe5cb55
|
Fixed some lint errors in derived configs
|
2024-01-31 11:39:59 -08:00 |
|
Rose Thompson
|
aa15a63d9c
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-01-31 13:12:32 -06:00 |
|
David Harris
|
91e21f5a85
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-01-30 08:53:18 -08:00 |
|
David Harris
|
06778088ab
|
Merge pull request #603 from stineje/main
Update cvt bug that was caught with new testbench-fp
|
2024-01-30 08:52:01 -08:00 |
|
James E. Stine
|
7e036e6f75
|
Update cvt bug that was caught with new testbench-fp
|
2024-01-30 10:51:07 -06:00 |
|
David Harris
|
f37c7bb1f6
|
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
|
2024-01-30 06:27:18 -08:00 |
|
David Harris
|
3db5b6d9a9
|
Fix FLI to support quads
|
2024-01-29 14:51:21 -08:00 |
|
Rose Thompson
|
e3574238a7
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-01-29 13:18:16 -06:00 |
|
David Harris
|
45e2317636
|
Added Wally github address to header comments
|
2024-01-29 05:38:11 -08:00 |
|
David Harris
|
e8dde265be
|
More coverage: CacheWay
|
2024-01-26 16:14:36 -08:00 |
|
David Harris
|
3620a10c0b
|
Improved hptw and I CacheWays coverage
|
2024-01-26 14:55:51 -08:00 |
|
Rose Thompson
|
cbc44a68ab
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-01-26 12:50:36 -06:00 |
|
David Harris
|
1c1d3eb956
|
HPTW coverage improvements
|
2024-01-26 10:46:38 -08:00 |
|
Rose Thompson
|
c0e04dd622
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-01-26 10:09:44 -06:00 |
|
David Harris
|
2449e06e55
|
Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported
|
2024-01-25 21:03:41 -08:00 |
|
David Harris
|
17f579d4ba
|
Reenabled fmadd.h, which is really supported by Zfh
|
2024-01-24 07:46:50 -08:00 |
|
Rose Thompson
|
117ff1828a
|
Merge pull request #590 from openhwgroup/revert-589-shiftcorrectiondebug
Revert "more shiftcorrection bug fixes"
|
2024-01-23 16:05:30 -06:00 |
|
Rose Thompson
|
d5bbb5ea27
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-01-23 14:37:11 -06:00 |
|
David Harris
|
4ffa5e7b0a
|
Coverage improvements
|
2024-01-22 09:49:24 -08:00 |
|
David Harris
|
171430a695
|
FPU and PMP tests
|
2024-01-21 14:41:22 -08:00 |
|
David Harris
|
ff055c404c
|
fpu coverage improvements
|
2024-01-21 13:17:56 -08:00 |
|
David Harris
|
9d4a14b209
|
coverage improvements
|
2024-01-21 11:39:51 -08:00 |
|
David Harris
|
d801bf5d6c
|
Revert "more shiftcorrection bug fixes"
|
2024-01-21 10:41:14 -08:00 |
|
David Harris
|
9e6fa8076f
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-01-21 10:15:38 -08:00 |
|
Kevin Kim
|
1459943a75
|
more shiftcorrection bug fixes
|
2024-01-21 10:08:48 -08:00 |
|
David Harris
|
69218b4b86
|
Coverage improvements
|
2024-01-21 10:03:07 -08:00 |
|
David Harris
|
17c9be7695
|
Cleanup typos, remove Zicond from riscof until it is working
|
2024-01-18 21:36:52 -08:00 |
|
David Harris
|
911b400af2
|
Fault on misaligned AMO
|
2024-01-18 13:13:56 -08:00 |
|
Rose Thompson
|
4c2ba2b0b4
|
Added StoreStall back to csrc.
|
2024-01-18 14:43:34 -06:00 |
|
Rose Thompson
|
81d006536a
|
Lint passes with 32-bit no D$, but many regressions fail.
|
2024-01-18 09:48:44 -06:00 |
|
David Harris
|
d5e102d520
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-01-18 07:38:25 -08:00 |
|
Rose Thompson
|
ff6bb3be0c
|
Fixed another bug with virtual memory and no caches.
|
2024-01-18 09:29:52 -06:00 |
|
Rose Thompson
|
e8474373e4
|
Fixed it so Virtual Memory work without a D$.
|
2024-01-18 09:18:17 -06:00 |
|
David Harris
|
74b242ce5c
|
Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
|
2024-01-17 12:25:06 -08:00 |
|
Rose Thompson
|
2d3dc55986
|
Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.
|
2024-01-17 12:19:10 -06:00 |
|
David Harris
|
4cfc86140c
|
Zfa fmvh complete and passing tests:
|
2024-01-17 06:18:00 -08:00 |
|
David Harris
|
07e7e02241
|
Coded Zfa fmvp but no tests exist
|
2024-01-16 21:26:42 -08:00 |
|
David Harris
|
8654375f26
|
Zfa fminm/fmaxm/fltq/fleq implemented and tested
|
2024-01-16 20:03:54 -08:00 |
|
David Harris
|
9d57002c07
|
Zfa fli support working for F and D (add fli.sv module)
|
2024-01-16 17:27:59 -08:00 |
|
David Harris
|
0588d611ea
|
Zfa fli support working for F and D
|
2024-01-16 17:27:40 -08:00 |
|
Rose Thompson
|
ed0f0d924b
|
Merge pull request #577 from davidharrishmc/dev
Zfh fix and typo corrections
|
2024-01-16 14:23:23 -06:00 |
|
David Harris
|
846a0c4d50
|
Check fma operations don't support H precision
|
2024-01-16 11:12:06 -08:00 |
|
David Harris
|
1a77c08f6e
|
Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
|
2024-01-16 10:46:44 -08:00 |
|
David Harris
|
dcd40c6be7
|
Fixed spelling of output
|
2024-01-16 10:27:31 -08:00 |
|
David Harris
|
abecc98563
|
Fixed spelling of precision
|
2024-01-16 10:26:00 -08:00 |
|
Rose Thompson
|
ff5554ca61
|
Atomics work correctly without a d cache.
|
2024-01-16 10:43:20 -06:00 |
|
Rose Thompson
|
dfe5ef4427
|
Added logic for the non-cache atomics.
|
2024-01-15 17:47:17 -06:00 |
|
Rose Thompson
|
82a786f185
|
Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.
|
2024-01-15 17:36:01 -06:00 |
|
Rose Thompson
|
614a83331f
|
Fixed part of issue #405.
The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
|
2024-01-15 17:29:00 -06:00 |
|
Rose Thompson
|
83df3dfe83
|
Fixed the zifencei bug (part of issue 405).
|
2024-01-15 16:02:37 -06:00 |
|
David Harris
|
0235970313
|
Optimized away unused support for fmv with quads
|
2024-01-15 13:40:12 -08:00 |
|
David Harris
|
da4eca4854
|
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
|
2024-01-15 13:24:57 -08:00 |
|
David Harris
|
9e78a7e290
|
Incorporated jstine fixes of FPU special case and testbench for conversion
|
2024-01-15 07:25:08 -08:00 |
|
David Harris
|
ed9fa07ba3
|
tests/coverage/tlbmisc.S
|
2024-01-15 07:16:11 -08:00 |
|
David Harris
|
fd181169fe
|
Corrected spelling of negative
|
2024-01-15 07:15:23 -08:00 |
|
James E. Stine
|
b14cd67bef
|
Values for IEEE 754 vs. RISC-V Table 11.4 in the RISC-V Unprivileged ISA
|
2024-01-14 22:08:42 -06:00 |
|
Jordan Carlin
|
51f670c821
|
Merge branch 'openhwgroup:main' into main
|
2024-01-12 19:43:01 -08:00 |
|
Rose Thompson
|
dd5f69cb78
|
Merge pull request #565 from davidharrishmc/dev
Dev
|
2024-01-12 21:30:27 -06:00 |
|
Jordan Carlin
|
092d10a3cd
|
correct c.sext.b encoding and remove unreachable code in 01100 case
|
2024-01-12 19:09:10 -08:00 |
|
David Harris
|
d7b016e8f3
|
Cleaned up Zicond implementation
|
2024-01-12 18:12:52 -08:00 |
|
David Harris
|
6226c3db96
|
Revert "Fixes for Issue #541"
|
2024-01-12 07:50:13 -08:00 |
|
James E. Stine
|
e707eeb7c8
|
THis includes fix for special case when conversion from fp to int/long. The previous src did not test both the flags and result and so missed this subtle bug when an Invalid happens for this type of conversion. These results are indications of undefined behavior for these operations. All fp operations now passs when this update is fixed. Much of the information why these outputs should occur is somewhat alluded to by Pascal Cuoq originally from INSA in Lyon here: https://frama-c.com/2013/10/09/Overflow-float-integer.html
|
2024-01-12 00:37:50 -06:00 |
|
Rose Thompson
|
ceae2bc714
|
Merge pull request #561 from davidharrishmc/dev
Added Zicond support
|
2024-01-11 10:20:01 -06:00 |
|
David Harris
|
9eb6d9c8b8
|
Added Zicond support
|
2024-01-11 07:37:15 -08:00 |
|
Rose Thompson
|
a932bf6b66
|
Removed unnecessary spill for compressed aligned to end of cache line or uncached access.
|
2024-01-10 13:06:16 -06:00 |
|
Rose Thompson
|
588e1caeba
|
Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.
|
2024-01-06 22:29:16 -06:00 |
|
David Harris
|
67124b0c7f
|
Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough
|
2024-01-06 07:11:25 -08:00 |
|
David Harris
|
0781cd4a44
|
Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate
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2024-01-05 22:45:15 -08:00 |
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Rose Thompson
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1f3792c823
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Fixed bug # 547, but there are other bugs which follow.
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2024-01-05 23:32:10 -06:00 |
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Rose Thompson
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edc56c669e
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Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
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2024-01-05 17:10:14 -06:00 |
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David Harris
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680a014876
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Finished LSU tlbcontrol coverage tests
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2024-01-02 10:16:20 -08:00 |
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David Harris
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d229dc06ee
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Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
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2024-01-02 00:35:17 -08:00 |
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David Harris
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f4ee05e1ea
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Coverage improvements
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2024-01-01 08:31:09 -08:00 |
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David Harris
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e5ac2d5ef0
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Modified align fsm to make coverage easier
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2024-01-01 08:21:31 -08:00 |
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David Harris
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6181639003
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Named IFU decomp generate block
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2024-01-01 07:37:40 -08:00 |
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David Harris
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c52aef86a6
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Fixed coverage exclusions that no longer reference code properly
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2023-12-31 20:35:08 -08:00 |
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David Harris
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8795a9db7a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-12-31 20:26:47 -08:00 |
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