David Harris
325ec4c8c8
Removed obsolete utility
2024-05-03 10:58:44 -07:00
David Harris
e667adf946
Added covergen directed coverage generator
2024-05-01 14:47:37 -07:00
David Harris
b7e66ec7d6
Added Zcb tests to riscof
2024-04-20 13:17:33 -07:00
Jordan Carlin
6ef6bc042d
Update RISCOF ISA config MISA values to be consistent
2024-04-06 18:18:50 -07:00
Rose Thompson
b87cdd49a3
Merge pull request #690 from davidharrishmc/dev
...
fcvt.h.l fixes, removed delays
2024-03-28 13:42:41 -05:00
David Harris
2b29b107a7
Wrote initial covergen for a few R-type instructions
2024-03-27 16:22:13 -07:00
Rose Thompson
7c3e93bb2c
added lpddrtest.
2024-03-26 18:42:48 -05:00
David Harris
4eb7de7381
Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test
2024-03-26 13:58:59 -07:00
David Harris
6688577bc4
Fixed fcvt test macro
2024-03-25 12:21:15 -07:00
David Harris
690338b758
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
2024-03-25 06:08:27 -07:00
David Harris
b3661a0af4
Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
2024-03-24 12:31:49 -07:00
Rose Thompson
e97c2cbd83
Merge pull request #676 from davidharrishmc/dev
...
Incorporated Zfa and Zfh tests into wally-riscv-arch-test, mcmodel example code, minor cleanup
2024-03-20 09:45:39 -05:00
Kevin Kim
d790a88277
fixed bug in intdivrem test vector extraction
2024-03-17 14:47:37 -07:00
David Harris
9ff9f9e0ae
Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
2024-03-14 19:03:57 -07:00
David Harris
48799aa87c
Added Zfh and Zfa tests to wally-riscv-arch-test until they are accepted in riscv-arch-test repo
2024-03-14 10:49:36 -07:00
David Harris
5e3ff3e871
Merge pull request #671 from Karl-Han/increase_riscof_jobs
...
Increase number of jobs in riscof to speedup building.
2024-03-13 14:52:05 -07:00
Kunlin Han
b5419ccfc9
Increase number of jobs in riscof to speedup building.
2024-03-13 12:28:30 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
Rose Thompson
402d71e5f4
Added basic Quad testing.
2024-03-07 15:19:53 -06:00
Rose Thompson
a85ace87c7
Sold progress towards a decent q test.
2024-03-07 15:01:48 -06:00
Rose Thompson
1872966b0b
Progress.
2024-03-07 13:02:24 -06:00
Rose Thompson
24dffa39d5
Yay. David and I got our first Quad load/store instructions working!
2024-03-07 12:48:52 -06:00
Rose Thompson
60f96112db
Moved the zero stage boot loader to the fpga directory.
2024-03-01 10:23:55 -06:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
James E. Stine
0d4d996655
add spike riscof items for K extension test
2024-02-24 22:43:33 -06:00
David Harris
824bc0dab7
Fixed expected value on WALLY-satp-invalid
2024-02-16 11:12:57 -08:00
Rose Thompson
6110799a1e
Updated the wally rv32 priv tests to not use sail.
2024-02-16 11:39:06 -06:00
David Harris
b362320dd9
Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
2024-02-16 06:46:49 -08:00
David Harris
d094201362
Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail
2024-02-16 06:27:49 -08:00
David Harris
9ba35991e3
Finished FPU coverage
2024-02-15 20:01:28 -08:00
harshinisrinath
86c35bad9f
Wrote illegal instructions for remaining floating point instructions
2024-02-07 17:13:49 -08:00
harshinisrinath
96c8526754
Wrote illegal instructions for remaining floating point instructions
2024-02-07 17:08:19 -08:00
David Harris
e7364290e3
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
2024-02-07 06:27:53 -08:00
David Harris
dfee790ad7
Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet.
2024-02-06 12:35:56 -08:00
David Harris
5d8d82414b
Coverage improvements
2024-02-04 11:40:38 -08:00
Jordan Carlin
2dce774d34
tlb ramline coverage improvements
2024-02-03 09:50:15 -08:00
Jordan Carlin
0312476fb3
Update tlb camline ASID coverage to use single file
2024-02-03 09:48:57 -08:00
Jordan Carlin
8633f263a2
Complete coverage of tlb camlines in IFU
2024-02-01 20:41:05 -08:00
Rose Thompson
87d91c5b14
Coverage updates.
2024-02-01 12:12:01 -06:00
Rose Thompson
ccf61853cf
New coverage for ebu.
2024-01-31 14:55:25 -06:00
Rose Thompson
07d1a4104a
Improvement to ebu coverage.
...
Also modified object dumps to include data segments.
2024-01-31 14:03:27 -06:00
David Harris
d9003da8e0
Moved some tests to wally-riscv-arch-test list that are simulated
2024-01-30 10:28:51 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
David Harris
3620a10c0b
Improved hptw and I CacheWays coverage
2024-01-26 14:55:51 -08:00
David Harris
1c1d3eb956
HPTW coverage improvements
2024-01-26 10:46:38 -08:00
David Harris
2449e06e55
Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported
2024-01-25 21:03:41 -08:00
David Harris
0e1c53f9f6
Fixed tlbmisc testing with PBMTE = 0
2024-01-24 12:24:33 -08:00
David Harris
66a1edb261
More coverage touchup
2024-01-23 23:11:49 -08:00
David Harris
7215f48dda
coverage improvements: fixing problems running ImperasDV on coverage tests
2024-01-23 22:21:01 -08:00
David Harris
d5f497eec5
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-22 09:56:50 -08:00
Jordan Carlin
0c13e14bbf
coverage improvements for mret when mpp = 3; update imperas config
2024-01-22 09:52:58 -08:00
David Harris
4ffa5e7b0a
Coverage improvements
2024-01-22 09:49:24 -08:00
Jordan Carlin
4936496bb9
fix sfence.inval.ir and sret coverage from previous PR
2024-01-22 08:58:31 -08:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
ff055c404c
fpu coverage improvements
2024-01-21 13:17:56 -08:00
David Harris
69218b4b86
Coverage improvements
2024-01-21 10:03:07 -08:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
13de147c7e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-18 22:12:07 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
Jordan Carlin
82d9467eea
Add coverage of FIOM in different privelege modes
2024-01-18 19:29:16 -08:00
Jordan Carlin
12b2baff82
add coverage of sfence.inval.ir instruction and fix sret coverage
2024-01-18 17:33:59 -08:00
naichewa
8b60992e72
fixed SPI tests failing when no icache
2024-01-17 14:38:11 -08:00
David Harris
f8c88a398a
Coverage improvements
2024-01-15 07:16:41 -08:00
Jordan Carlin
51f670c821
Merge branch 'openhwgroup:main' into main
2024-01-12 19:43:01 -08:00
Jordan Carlin
6c797570fa
Add coverage for all Zcb instructions
2024-01-12 19:10:13 -08:00
Rose Thompson
0b2af0c99a
Modifed the sv39 tests so they work with just 128MiB physical memory.
2024-01-12 20:00:21 -06:00
Rose Thompson
e6a2595936
Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
2024-01-12 11:05:06 -06:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
ba7e017bd9
Added Zcb c.lbu coverage test
2024-01-10 10:01:46 -08:00
David Harris
d36b6e919a
Fixed missing Zba ISA string from spike_rv64gc_isa.yaml for RISCOF
2024-01-09 10:00:06 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
0781cd4a44
Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate
2024-01-05 22:45:15 -08:00
David Harris
ed623f1a71
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
2024-01-05 20:06:21 -08:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
b025cd8a0d
Updated tlbNAPOT to test instructions as well
2023-12-20 23:01:35 -08:00
David Harris
9ced88c55c
Fixed tlbNAPOT test to run and makefile to gather coverage stats
2023-12-20 21:45:14 -08:00
David Harris
d130a78616
Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported
2023-12-20 16:29:03 -08:00
David Harris
0ff049db86
Removed unused tests from wally-riscv-arch-test
2023-12-20 13:34:12 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
49b1b7c7f9
Fixed the last uninitialized memory issue in the priv tests.
2023-12-19 16:51:56 -06:00
Rose Thompson
b04ad23c33
Fixed bugs in the wally64periph signature.
2023-12-19 16:16:59 -06:00
Rose Thompson
726efee1e2
Fixed bugs in the cbom test.
2023-12-19 15:53:48 -06:00
Rose Thompson
418ae0decc
Fixed some regression tests with David's help.
2023-12-19 14:18:21 -06:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
David Harris
166c98b6f6
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
2023-12-13 19:43:17 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
David Harris
0f0b4b0c1c
Added make wally-riscv-arch-test to tests/riscof to only build custom tests
2023-12-06 07:19:12 -08:00
David Harris
2b2016271a
repo cleanup and start to add CMO tests
2023-11-20 23:41:36 -08:00
Rose Thompson
540d8d930d
Cleanup.
...
Linux makefile
wally tracer. probably reduce some complexity here.
2023-11-13 14:04:43 -06:00
Rose Thompson
9dfe421c55
Yay! Zicclsm passes my regression test now.
2023-11-10 18:28:51 -06:00
Rose Thompson
c0e02ae190
Found another bug in the RTL's Zicclsm alignment.
2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
2023-11-10 17:58:42 -06:00
Rose Thompson
bd866e1025
Fixed some more bugs in the Zicclsm signature.
2023-11-10 17:36:10 -06:00
Rose Thompson
efecb0c346
Fixed bug in the Zicclsm test.
2023-11-10 17:34:23 -06:00
Rose Thompson
ada354f443
Fixed bug in the misaligned access test.
2023-11-10 17:02:15 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
naichewa
d67badfc60
fix hardware interlock, hold mode deassert
2023-11-08 15:20:51 -08:00
naichewa
a5837eb62c
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
naichewa
4651b807ed
added test cases
2023-11-02 15:43:08 -07:00
Rose Thompson
0a4ed5515b
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
afa1d85e3b
Doesn't yet fully work.
...
Thomas is going to finish debugging while I'm on the RISCV summit next week.
2023-11-02 12:07:42 -05:00
Rose Thompson
7ba891f607
Progress. I think the remaining bugs are in the regression test's signature.
2023-11-01 17:51:48 -05:00
naichewa
9aa8a7af3e
comments, more test cases
2023-11-01 01:26:34 -07:00
Rose Thompson
5660eff57d
Working through issues with the psill logic.
2023-10-31 18:50:13 -05:00
Rose Thompson
4984b3935f
Progress
2023-10-31 14:50:33 -05:00
Rose Thompson
5ca428d6a8
Fixed bugs in misaligned test.
2023-10-31 12:49:35 -05:00
Rose Thompson
c061440141
First stab at the misaligned test.
2023-10-31 12:30:10 -05:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63
hardware interlock
2023-10-30 17:00:20 -07:00
Rose Thompson
2241976d29
Updated mmu to not generate trap on cacheable misaligned access when supported.
...
Updated tests with David's help.
2023-10-30 18:26:11 -05:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
Rose Thompson
0fd5b3b2ce
Updated comments in the cboz tests.
2023-10-20 15:15:47 -05:00
Rose Thompson
5a4028064a
Updated comments for the cbom tests.
2023-10-20 15:13:52 -05:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
ac4216b43d
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
David Harris
6245748ed7
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
2023-10-15 15:31:03 -07:00
David Harris
b4891d88db
Added WALLY minfo test for rv32
2023-10-15 06:48:22 -07:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
f231c3d3a3
correct delay0, fmt register test entries
2023-10-12 15:13:23 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
9ff3642c6c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-05 11:12:00 -05:00
David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
1642ad2bad
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
Ross Thompson
12c3c98824
Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
2023-08-30 11:29:44 -05:00
David Harris
91429f3f02
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
0e16203cd8
Merge pull request #393 from ross144/main
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Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
cd3349bd26
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
7d51690b7c
Oups forgot to include the 32-bit cbom test in previous commit.
2023-08-24 09:04:41 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
David Harris
409abbf443
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
Ross Thompson
310b700550
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
Ross Thompson
5ed096e4bc
Made a bunch of progress towards getting cbo instructions tested.
2023-08-21 11:46:21 -05:00
harshinisrinath
3d3d15077b
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fdb7abec06
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
David Harris
2738423441
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
harshinisrinath
7494ce06eb
wrote testcase to write into FSCR
2023-08-20 12:10:08 -07:00
Ross Thompson
05d590b0b9
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9
Now we have invalidate, clean, and flush working.
2023-08-18 16:32:22 -05:00
Ross Thompson
4eeba9bed9
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
2023-08-18 15:59:39 -05:00
harshinisrinath
b4cfdf3393
Fixed bug and tried to reset menvcfg to improve testing of csri in priv.
2023-07-30 16:40:06 -07:00
harshinisrinath
413a104b6c
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-07-23 11:59:43 -07:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
harshinisrinath
8adfcebb4f
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-07-13 13:00:58 -07:00
Kevin Kim
f6a3474550
fixed bug in testvector extract script
...
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
2023-06-22 09:13:22 -07:00
harshinisrinath
f9d3944cc5
Improved testing of pmd in priv.
2023-06-16 17:13:54 -07:00
harshinisrinath
d018357914
Improve test coverage on ieu fw.
2023-06-16 16:09:48 -07:00
David Harris
c137a1c8cf
Fixed timer interrupt testing
2023-06-09 17:20:41 -07:00
David Harris
f68b9c224a
Fixed WALLY-trap test case to use menvcfg
2023-06-09 15:24:26 -07:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
Ross Thompson
4ddbbd6948
Merge pull request #314 from davidharrishmc/dev
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Make and FP script improvements
2023-06-06 12:38:26 -04:00
James Stine
ac3253203d
Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing
2023-06-05 11:03:59 -05:00
David Harris
1831dfccc2
Fixed paths in creating division test vectors
2023-05-31 06:30:41 -07:00
David Harris
b5f70013b1
Clean up combined int/fp vector creation
2023-05-30 14:01:12 -07:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
David Harris
b4c9998b26
Increased timeout for riscof because it is so slow
2023-05-23 15:37:09 -07:00
David Harris
19096a812a
Added Zifencei ISA to tests where necessary to support new compiler
2023-05-16 11:18:27 -07:00
David Harris
0a7a159d69
Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
2023-05-14 06:58:29 -07:00
David Harris
0cc8f9fd15
Fixed riscof scripts that were removing zicsr from compiler misa
2023-05-14 04:19:08 -07:00
David Harris
67a089104c
Defined empty RVMODEL interrupt macros to make riscof warnings go away
2023-05-14 03:36:28 -07:00
Kevin Thomas
0c9b7dcce7
Comment tlbGBL more discriptively
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Reduce redundant instructions
2023-05-04 19:13:47 -05:00
David Harris
ec3518673e
Merge branch 'main' into main
2023-04-28 07:51:32 -07:00
Liam Chalk
028d19bbfa
Merge branch 'main' into main
2023-04-27 21:49:01 -07:00
Kevin Wan
39c9cd5ee9
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
David Harris
15fb5fa2ac
Update tlbASID.S
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fixed comment about restoring ASID to 0
2023-04-27 14:32:57 -07:00
Noah Limpert
4ec31de316
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Alexa Wright
09095422d0
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
59d913949f
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Liam
7bf2ee5418
pmpaddr0 and pmpaddr2 test cases
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Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
2023-04-25 15:37:04 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Liam
c2f441724b
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
d74768ce04
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d
a
2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
