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Added Zifencei ISA to tests where necessary to support new compiler

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This commit is contained in:
David Harris 2023-05-16 11:18:27 -07:00
parent 1b385c4336
commit 19096a812a
19 changed files with 19 additions and 18 deletions
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1
setup.sh
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@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY}
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin
#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim # Change this for your path to Questa, excluding bin
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
# Path to RISC-V Tools

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
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@ -36,7 +36,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
.equ UART, 0x10000000

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
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@ -35,7 +35,7 @@
#define PLIC_RANGE 0x03FFFFFF
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
INIT_TESTS