cvw/tests
Alec Vercruysse cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
..
coverage Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 2023-04-19 01:34:01 -07:00
custom *.out removal 2023-04-05 12:50:26 -07:00
fp integrated tv generation for IFdivsqrt 2023-03-29 20:57:26 -07:00
riscof Removed unused ISA string from spike YAML 2023-03-22 13:23:52 -07:00
testgen Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
wally-riscv-arch-test restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00