mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
fixed SPI tests failing when no icache
This commit is contained in:
parent
ed0f0d924b
commit
8b60992e72
@ -607,6 +607,7 @@ SETUP_PLIC
|
||||
.4byte delay1, 0x0000001, write32_test # reset delay1 register
|
||||
.4byte cs_mode, 0x00000000, write32_test # reset cs_mode
|
||||
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
.4byte sck_div, 0x00000100, write32_test # lower SPI clock rate so read32_tests trigger at correct times
|
||||
#.4byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
|
@ -608,6 +608,7 @@ SETUP_PLIC
|
||||
|
||||
.8byte delay1, 0x0000001, write32_test # reset delay1 register
|
||||
.8byte cs_mode, 0x00000000, write32_test # reset cs_mode
|
||||
.8byte sck_div, 0x00000100, write32_test # lower SPI clock rate so reads are done at correct time when ICACHE not supported
|
||||
.8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
#.8byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
|
Loading…
Reference in New Issue
Block a user