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Fixed tlbmisc testing with PBMTE = 0

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This commit is contained in:
David Harris 2024-01-24 12:24:33 -08:00
parent 17f579d4ba
commit 0e1c53f9f6
1 changed files with 7 additions and 3 deletions
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10
tests/coverage/tlbmisc.S
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@ -104,14 +104,17 @@ main:
# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
li t0, 0x80805000
jalr ra, t0
li t0, 0x80807000 # again, triggering setting access bit
jalr ra, t0
# Good PBMT with menvcfg.PBMTE = 0
li t0, 3
li a0, 3
ecall # switch to machine mode
li t5, 0x1
slli t5, t5, 62
csrc menvcfg, t5 # menvcfg.PBMTE = 0
li t0, 1
li a0, 1
ecall # switch back to supervisor mode
li t0, 0x80806000
jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
@ -365,6 +368,7 @@ pagetable:
.8byte 0x00000000200000C3 # valid r for VA 80802000
.8byte 0x00000000200000C9 # valid x for VA 80803000
.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
.8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA
.8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate
.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
.8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA